Design And Implementation Of Deep Neural Network For System On Chip

With the rapid development of semiconductor manufacture,integrated circuits can merge many functions such as signal acquisition,processing,storage and I/O on a single chip.This system-level integrated circuit is also named SoC(System on Chip).SoC implements almost all system-level functional modules on a single chip.It has the characteristics of high speed,high integration and low power consumption.At the same time,it reduces the volume and cost of products largely.Therefore,SoC is widely used in communication,control,multimedia and other fields.Deep neural network has made many breakthroughs in image detection,speech recognition,natural language processing and many other fields of artificial intelligence.As the deep neural network becomes more and more complex,its requirement for computational ability becomes higher and higher.However,there are strict performance and power constraints for SoC because it is mostly used in embedded systems.Therefore,how to apply neural networks to SoC(embedded systems)has become an urgent problem to be solved.This paper studies the application of neural networks in SoC from the following three aspects:Firstly,SoC is a highly integrated embedded system.Due to the limitations of area and power consumption,SoC usually applies deep neural network by training model in cloud and then migrating to embedded devices.This paper proves the necessity of local retraining by apply a deep neural network pre-trained on public data sets on personalized data sets.To solve the problem that it is difficult to collect labelled data in local retraining process,this paper proposes a training method based on user's correctness feedback.Although it is difficult to ask users to specify the label of a training case manually,users can give a feedback to the prediction results of the neural network,“prediction correct" or " prediction error",and then generate a fake label according to user's feedback.Then the fake label can be used for training the neural network.Secondly,compared with the layer-based accelerator design,the neural network accelerator based on domain specific instructions has the characteristics of high flexibility and strong expansibility.However,the implementation of an independent accelerator requires additional hardware and software resources such as decoding units and compilers.This paper proposes that using custom instructions to design the specific instructions,so that the accelerator and CPU share the decoding unit and the compiler.Meanwhile,they are tightly coupled by the coprocessor interface,which has higher communication efficiency.Thirdly,fixed-point representation occupies less memory space and the calculation circuit is simple to implement compared with floating-point representation,so the accelerator implementation in this paper uses 8-bit signed fixed-point representation.However,the decimal places of fixed-point number is fixed and the dynamic range of the representation are limited,so the calculation results can easily exceed the representation range.In order to solve this problem,a dynamic mechanism is introduced tofixed-point representation in this paper,i.e.the decimal places of elements in each vector are the same,and the decimal places of different vectors can be different.This allows the decimal places to be set according to the data range of each vector.