An Efficient General Accelerator For Convolutional Neural Network

For accelerators in embedded system,it's important to improve the running speed of convolutional neural network and reduce the running energy consumption under the condi-tion of ensuring the accuracy of the running result.Meanwhile,due to the lack of unified accelerator architecture and software development environment,researchers get difficult trial in the tasks of transplanting convolutional neural network on accelerator.In this thesis,a set of high-level instructions for convolutional neural networks is pro-posed,and based on this set of instructions,a general purpose accelerator architecture with high parallelism,high configuration and low power consumption for convolutional neural network is designed.In order to facilitate transplantation of convolutional neural networks,most network models can be transformed into a fixed instruction sequence,and get right results on the accelerator through the operations of instruction fetching,decoder,and ex-ecution.At the same time,the accelerator is equipped with 8 SRAM for kernel weights,and each of them is directly connected to a PE unit,so that the PE array can get high parallelism with distribution of kernel weights to achieve the calculation.Considered the similarity of convolutional layer and FC layer,the accelerator support both layer calculation with same PE array.Through instruction configuration,the accelerator supports 8bit/16bit mixed precision of convolutional network model.To make full use of data sparsity,a com-pression/decompression method for high sparse data has been executed on the accelerator can achieve to reduce the pressure of data bus.The architecture is implemented successfully on FPGA and runs Lenet-5 and Alexnet network.Experiments show that the accelerator architecture proposed in this paper has some advantages in performance and power consumption.The accelerator exhibits wide adaptability and support for general convolutional neural networks.