Research On Neural Network Accelerator Based On Network-on-chip

The rapid development of chip technology makes it possible to integrate multiple processing units in a chip.Network-on-Chip(No C)is considered as an interconnected communication architecture for multi-core systems.And other aspects are superior to traditional buses.Neural networks have been widely used in artificial intelligence applications,such as image processing,speech recognition,machine translation,etc.Contemporary artificial neural networks include dozens of layers and millions of parameters.Neural networks have become more complex and the amount of calculations has increased dramatically.Conventional traditional computers take a lot of time.In order to solve these problems,people have accelerated the neural network by improving the structure of general-purpose chips and developing special neural network accelerators,also known as artificial intelligence chips.Since not only complex interconnections but also intensive calculations and communications exist between the neurons of a neural network,modern neural network intensifiers are mostly composed of numbers of processing units.The communication architecture between them uses a No C to realize data transmission between neural networks.Therefore,research on how to implement various aspects of network-on-chip has become an important direction for optimizing neural network accelerators based on No C.In the process of studying the neural network accelerator based on No C,this article mainly optimizes the neural network accelerator based on No C from the mapping and topology of network on chip.Focused on the mapping algorithm based on 3D No C,and proposed a Hybrid Chaotic Big Bang Algorithm(HCBB-BC)to solve the 3D No C mapping problem,and compared with the classic genetic algorithm and particle swarm algorithm,whether it is under the classic task map mapping or Under the neural network topology mapping,the algorithm can achieve faster convergence speed and reduce power consumption.Based on this,this paper proposes to apply a neural network accelerator to a 3D Mesh No C topology,which can have lower power consumption than a neural network accelerator based on a 2D Mesh No C topology,while using a HCBB-BC mapping The algorithm can further reduce the power consumption of the neural network mapping.