Design Of Neural Network Accelerator For Portable Applications

In recent years,the rapid development of semiconductor technology makes the number of transistors in the chip increase rapidly.With the support of large-scale highspeed computing platform,deep neural network(DNN)technology has made great progress.Common DNN operations consist of two stages,inference and training.For users,the structure and parameters of the DNN need to be updated during daily use.Given the advantages of the above DNN real-time updating model,it is necessary to combine inference and training in one single neural network accelerator.The main tasks are as follows:1.Deeply analyze the operations involved in the inference and training of deep neural networks,then abstract them into mathematical models,and propose an acceleration method for different types of operations.This paper focuses on the analysis of the parameter updating process during training phase,and puts forward the hardware acceleration method for matrix transpose multiplication operation and convolution operation involving large convolution kernel.After proper adjustment and algorithm adaption,the processor can be compatible with all kinds of computations.2.Two convolution acceleration algorithms are implemented using hardware circuits.According to the characteristics of two kinds of convolution operations in the process of inference and training,convolution reduction and matrix multiplication are used to accelerate the convolution,and build the discrete cache structure on the chip to prepare the data for achieve efficient algorithm implementation.3.Design a reconfigurable calculator array adapted to various operation types,the discrete data cache structure on the chip is constructed in each calculator unit,which reduces the data interaction between the system and the off-chip memory,and improves the data reuse rate.We use instructions to control the register address rules,data paths,and processing functions,so the array can be used in many calculation demands.4.For different operation modes,we can design a general computation array and complete the hardware implementation,and carry out functional verification and performance testing on the FPGA chip.We designed three experiments,like single instruction test,handwrite digital number recognition,and auto-pilot decision network,and finally,we obtained the test results of system implementation and accelerator performance.