Design Of General-purpose Convolutional Neural Network Accelerator Based On FPGA

In recent years,neural networks have demonstrated excellent performance in areas such as target tracking,speech detection and recognition,unmanned driving,and combating epidemics.Convolutional Neural Networks(CNN)is one of the most widely used neural networks.However,general-purpose computing platforms such as CPUs and GPUs cannot meet the computing needs of deep learning in terms of performance and power consumption.The neural network accelerator of the ASIC platform is less flexible and cannot meet the computing needs of different application scenarios for neural networks.The design difficulties of convolutional neural network accelerators are: 1)the number of layers in different networks is different;2)the type of layers is different;3)the parameters of different layers are diverse,and the amount of data and parameters are large.In other words,the above three difficulties pose extremely high requirements for the flexible design of convolutional neural networks.Therefore,exploring the general architecture of the configurable convolutional neural network accelerator on the FPGA platform and meeting the needs of specific applications in terms of performance,area,and power consumption has a broad research space.In summary,this thesis will focus on the discussion and discussion of the design method of general convolutional neural network accelerators,and propose design and optimization methods for the softmax function in neural networks.In addition,this thesis proposes solutions for the unmanned driving field with high current attention.The main work of this thesis is as follows:1.Design the hardware architecture of general convolutional neural network accelerator.Specifically,the universal computing unit supports any size and any number of convolution kernels in the convolutional layer and any number of neuron operations in the fully connected layer.Based on the general computing unit,a general convolutional neural network accelerator hardware architecture is designed here.2.Propose softmax hardware architecture with configurable precision.This thesis summarizes the general rules of neural network classification,and effectively solves the problem of excessive input range of softmax layer.In addition,this paper proposes an exponential function calculation unit with variable calculation accuracy and improves a natural logarithm function calculation unit based on the first two items of Mac Laurin series.The calculation accuracy of the exponential function calculation unit can be freely adjusted in 23-bit,35-bit and 42-bit precision.The improved natural logarithm function calculation unit reduces the calculation accuracy of 2-32 bits in the original design to 15-25 bits.3.Design an FPGA-based verification platform for driverless systems.In view of the unsuitable and over-ideal data sets in related work,neural network structures with large network size and many weight parameters,and ASIC accelerators with large resource consumption and high manufacturing costs,this paper proposes data enhancement methods to make data sets and explore simplified versions Neural network architecture and hardware level integrate multiple neural networks into the same hardware architecture.This paper designs a simulation of road traffic scenes,and collects scene information through the camera to direct the smart car model to complete the corresponding actions.