Design And Implementation Of Neural Network Convolution Coprocessor Based On RISC-V

As an important branch of artificial intelligence,deep learning has developed rapidly in recent years and has attracted widespread attention at home and abroad.Among them,Convolutional Neural Network(CNN)is one of the most widely used architectures in deep learning,and has been widely used in many fields such as speech recognition,image recognition,and image processing.The traditional GPU / CPU-based software implementation is not fast enough to meet the needs of applications such as mobile phones.This paper studies and implements the CNN coprocessor based on risc-v architecture for convolutional neural network.After in-depth study of various convolutional neural networks,this paper conducted a modeling and simulation experiment on a classic neural network algorithm.It was found that the convolution operation as the core of the CNN algorithm occupied more than 90% of the operation amount.Moreover,the convolution operation At its core,matrix multiplication and accumulation can further refine atomic operations.Therefore,based on the RISC-V architecture,this paper designs a coprocessor that supports CNN enhancement.In order to improve performance,this article first adds related instructions of the convolutional neural network based on the RISCV instruction set extension and performs the corresponding matrix operation kernel unit.,Instruction decoding,execution,and other circuits;at the same time,in order to further increase the operation speed and reduce the access time,pipeline design is performed in functional modules such as the arithmetic unit,and high-throughput tightly coupled memory design is also implemented;The extended instruction is a multi-cycle instruction,which requires multiple cycles to complete and write back,which will cause data correlation problems in the pipeline structure of RISC-V.This article is also in the instruction dispatch stage to implement a pipeline conflict correlation detection circuit and respond accordingly.Accelerate and optimize the flow.After the circuit design is completed,the UVM platform is set up to verify the function of the circuit.Finally,the circuit is synthesized based on the SMIC 110 nm process.The CNN coprocessor designed in this article is the 40423 equivalent gate.In addition,we The data rate test comparison before and after the design of the CNN coprocessor is also performed.The general-purpose processor of the RISC-V architecture that does not support the CNN function is selected for the hummingbird processor.The test results show that the CNN coprocessor designed in this paper greatly improves the data processing speed and can meet the needs of the application under the condition that the acceptable chip area increases.