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Research And Hardware Implementation Of Bistatic SAR Imaging Algorithm

Posted on:2020-07-02Degree:MasterType:Thesis
Country:ChinaCandidate:W HuangFull Text:PDF
GTID:2428330596476150Subject:Signal and Information Processing
Abstract/Summary:PDF Full Text Request
Bistatic sythetic aperture radar(BiSAR)can achieve forward-looking imaging and its receiver can be silence due to its transmitter and receiver mounted on different platforms.Therefore,it has wide fields in application and broad research value.Since the transmitter and receiver of Bistatic sythetic aperture radar are independent,the imaging process of it is more complicated and the amount of calculation of BiSAR makes it difficult to process image real-time.This thesis realized a radar signal processor with FPGA and DSP and completed the design of it based on the application requirements of BiSAR real-time processing.Then the related algorithm is transplant successfully.These works have verified by software and hardware simulation and the main interface of the radar signal processor tested.The main work is as follows:1.Aiming at the shift invariant,an echo model of BiSAR is Established first.Then analyze the two-dimensional spectrum by principle of series reversion.Gives the implementation steps of the time-domain imaging algorithm FFBT with its self-focusing algorithm and frequency-domain imaging algorithm RD with PGA self-focusing algorithm.The computational complexity of the imaging algorithms are analyzed.2.Aiming at the problem of large amount of data and large amount of calculation of Bistatic SAR imaging processing,a signal processor with VPX structure is designed.It use FPGA and multi-block DSP as main processor.The specific detail design of the signal processing board and data acquisition board are given.3.Aiming st the characteristics of large amount of calculation.Based on the hardware architecture of multichip DSP of the signal processor,an implementation method of multi-DSP pipeline parallel processing is proposed and realized real-time processing of imaging and autofocus algorithm.4.Under the consideration of the hardware architecture of multi-core DSP TMS320C6678,a multi-core parallel processing implementation methods of RD imaging algorithm and phase gradient autofocus Self-focusing algorithm are proposed.
Keywords/Search Tags:Bistatic SAR, Radar Imaging, Signal processor, Field-Programmable Gate Array, Digital Signal Processor
PDF Full Text Request
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