Design And Development Of Missile Borne Radar Signal Processor System Based On FPGA

This paper mainly focuses on the design and development of the signal processor for a millimeter wave radar seeker. As the core component of a radar seeker, the signal processor deals with the processing of the received echo so as to detect and recognize the target to be attacked. Not only that, but it also generates relative orders to control the system operation according to detection results. With the rapid development of radar signal processing techniques, the computational complexity and data volume increase exponentially, which requires higher performance of the signal processor.Firstly, the design of the signal processor is accomplished, including the determination of the operation modes, transmitting waveforms, and the workflow of the signal processor. This radar seeker is designed to work at two operation modes, namely pulse Doppler (PD) and stepped frequency (SF). As the seeker works at millimeter wave band, a low target speed leads to large Doppler shift. Therefore, the mode of PD is adopted for moving targets, while the mode of SF for stationary or slow targets. At the mode of SF, the high resolution range profile (HRRP) of the target scene can be obtained by synthesizing multiple pulses, which facilitates the target detection and recognition. In addition, two transmitting waveforms are adopted to enlarge the action range of the radar seeker, including the simple pulse and linear frequency modulation pulse. Hence the signal processing procedure at different modes and the whole workflow of the signal processor can be determined.Secondly, a FPGA+DSP system architecture is selected to satisfy the requirement of small size, low power, and better performance, which is necessary for the radar signal processor due to the characteristic of missile-borne platform. A FPGA of the series of Virtex-6 from Xilinx is selected, while the DSP chip TMS320C6416 from TI is selected. In general, the data volume of bottom signal processing is so amount that it requires a higher computational speed. Besides, the calculation is relatively simple, such as pulse compression, pulse accumulation, FIR filtering, and CFAR, etc., which makes FPGA suitable for its hardware implementation. On the other hand, the top processing needs a small amount of data, but its control structure is relatively complex. Thus the DSP is adopted for its advantages of high speed, flexible addressing mode, and rich interface resources. With the task assignment of the signal processor, the system development of FPGA is finished according to the design rules of FPGA, combined with consideration of the maturity of the theoretic algorithms.Finally, according to the existing conditions, a feasible test and verification scheme is designed to validate the correctness of FPGA system.