Design And Implementation Of Rate Control Based On Video Array Processor

With the rapid development of 4G technology and Internet technology, the HEVC (High Efficiency Video Coding) studied by the JCT-VC has gradually become the necessary technology of the mainstream product, comparing with the previous video coding standards, which improves the efficiency of compression, but brings the increase of computational complexity at the same time. Those propose higher requirements for the video codec computational ability.After studying the requirements of video decoding algorithm for instruction transmission, this paper finished the design of the instruction transmission network of video processor array structure, the instruction transmission network is suitable for 32 X 32, that is 1024 thin-core process elements. Moreover, it supports single instruction single data stream (SISD) model also supports Single instruction multiple data stream (SIMD) mode. Using Verilog HDL to completed the design of circuit and ISE 14.7(64-bit) of Xilinx for integrating circuit, then testing the circuit by downloading it toVirtex6 series development board.In order to test the performance of reconfigurable video array processor, the rate control algorithm for HEVC is implemented on the structure. Rate control is the study of how to guarantee the quality of coding under the limited bandwidth is a very important problem because the bandwidth resource is limited. Rate control algorithm is an important way to improve the quality of coding transmission in video coding. After analyzing the rate control algorithm based on the R-λ mode proposed in TCTVC-K0103, this paper finished the calculated of the allocation of bits in the algorithm, the computation of Lagrange parameters and the quantization parameters in the programmable reconfigurable video array processor. To solve the problems of the transcendental function, the calculation method of coordinate rotation digital (CORDIC:Coordinate Rotation Digital Computer) is selected, and implemented on the structure, completed the function simulation and FPGA test. Finally, the rate control algorithm is implemented on the structure, then testing the circuit by downloading it toVirtex6 series development board. Experimental results show that compared with similar studies, obtained the good efficiency and when the algorithm needs to be improved, only need to improve the software program, improves the flexibility, while reducing the two R & D spending while increasing the prospects for market applications.