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Design And Implementation Of LDPC Coding And Decoding Circuit Based On DVB-S2 Protocol

Posted on:2019-07-07Degree:MasterType:Thesis
Country:ChinaCandidate:M LiuFull Text:PDF
GTID:2428330566996555Subject:Microelectronics and Solid State Electronics
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Since errors occur due to noise after the information passes through the channel,the forward error correction code is widely used in modern digital communication systems.The ideal case of concatenated code performance is to approach the Shannon limit,and the concatenated code is compared to a single error.Error code has certain superiority in performance.In the Digital Video Broadcasting Satellite Second Generation,a concatenated code error correction technique is also adopted.In DVB-S2,a concatenation of an outer code BCH and an inner code low-density parity check code is applied.This paper takes the LDPC code in forward error correction system of DVB-S2 protocol as the research background,and introduces the basic knowledge of LDPC code in detail.Then the general encoding method of linear block code and the encoding method given in DVB-S2 protocol are introduced.Decoding algorithms: log domain confidence propagation algorithm,normalized minimum sum algorithm,offset minimum sum algorithm and minimum sum algorithm are introduced in detail.The realization of the two coding algorithms finds that the coding method given in the DVB-S2 protocol has a linear coding complexity,so it is chosen to implement the circuit.For the decoding algorithm,except for the logarithmic domain algorithm,and software implementation,and then compare the number of iterations and error rate,and found that when the offset is better than the sum of 0.1,so the final selection offset The LDPC code decoder is implemented by selecting 20 iterations for 0.1 iterations.After the circuit implementation of the codec was simulated and synthesized using modulsim and Design Compiler,the simulation results were correct.The SMIC65 nm technology library was used synthetically.The total area of the coding circuit was 296.280 million square microns and the maximum clock frequency was 217 MHz.The total area of the decoding circuit is 259083.722161 square microns and the maximum clock frequency is123 MHz.In the DVB-S2 standard,the throughput rate is bigger than 128 kbps,and the throughput rate in this paper meets the requirements.
Keywords/Search Tags:forward error correction, DVB-S2 standard, low density parity check, belief propagation algorithm
PDF Full Text Request
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