The FPGA Design And Implementation Of Forward Error Correction Coding And Decoding Based On G3-PLC

In recent years,under the promotion of the technology of internet of things,the application of smart home is gaining more and more attention.Power line communication(PLC)refers to a communication technology which can realize data transmission on power line network.It has a series of advantages such as low cost,wide coverage,without rewiring etc.PLC has become one of the most efficient solutions for the application of smart home.But as the channel condition of power line is hostile,there are many kinds of interference which makes the reliability of communication under threat.In order to meet the communication requirements for high-speed and high reliability,the choice of communication standard is particularly important.G3-PLC is a narrowband power line communication standard proposed by G3 alliance in 2009,which combines Front Error Correction(FEC)and Orthogonal Frequency Division Multiplexing(OFDM)to realize the data transmission on power line with high-speed and reliable.This thesis aims is to implementation the FPGA design of the FEC based on G3-PLC.First,the paper makes a brief introduction of G3-PLC physical layer system.Then,the algorithm and realization of codec based on G3-PLC system is analyzed and researched deeply.In finite field multiplier,the paper proposes a kind of look-up table to realize the finite field multiplication and division operation,which has the merits of fast computing speed and simple structure.In RS decoder,the algorithm of Berlekamp-Masse iterative is optimized for rapidly obtain the correction term.In Viterbi decoder,in order to solve the problems of the traditional parallel structure,a kind of structure with partial parallel is designed.Based on the structure,the storage and reading logic of the path metric is simplified with the effectively allocate of the path metric.It can realize an effective compromise between area and speed by configurating the reuse times of butterfly processing element.In the interleaving codec,the paper adopts a static interleaving scheme,which can make interleaving algorithm easy for hardware implementation.The static interleaving scheme can realize interleaving and de-interleaving by configuring different interleaving tables.After that,the FPGA design of entire coding and decoding system is completed by the Verilog hardware description language,and the simulation is completed in the NC-Verilog Simulator.The timing simulation results prove the system can correct the error caused by the channel of power line.In the end,the hardware implementation of the design is carried out by using the FPGA platform and Vivado.The online test results prove the design can make a reliable data transmission on power line.