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Development Of 32-channel Parallel AD Module

Posted on:2020-06-25Degree:MasterType:Thesis
Country:ChinaCandidate:Z MengFull Text:PDF
GTID:2428330590995294Subject:Instrumentation engineering
Abstract/Summary:PDF Full Text Request
With the continuous development of automated testing technology,data acquisition module has been widely used in aerospace,industrial measurement and control and other fields.However,due to the increasing complexity of the number and nature of signals to be measured,most data acquisition modules are currently developed only for specific test requirements of dedicated systems.,The key parameters of data acquisition module,such as the number of measured signals,high sampling rate,high resolution,parallelism and types of supporting operating systems,are difficult to take into account.Therefore,a multi-channel parallel acquisition module based on CPCI bus is developed in this paper,which can meet the practical application requirements,It has a certain reference value for the design of the same type of data acquisition module.Firstly,the requirement of the module's technical specifications is analyzed.Combining with the possible application scenarios of the general test platform,the overall scheme of the 3U size CPCI data acquisition module with versatility,flexibility and maintainability is put forward,and the design are carried out from three aspects: hardware circuit,firmware logic and software driver.In the process of hardware circuit design,the parallelism function realization,card integration,module power consumption,PCB layout and wiring are fully considered.The hardware circuit determine the AD7771 analog-to-digital conversion chip as data acquisition core,FPGA as hardware control processing core and CPCI bus as data interaction core,realizing real-time acquisition,processing and transmission of multi-channel and multi-type input signals.In the process of firmware logic design,the logic reusability and design flexibility are fully considered.Custom IP cores are used to design the logic of each functional module.The design of high-speed data flow for parallel modules is described in detail.The bus interfaces of each functional module reserve the control and status register groups accessible by the host computer,which can complete good human-computer interaction.Finally realize the SOPC design with Avalon bus as the logic interconnect core and PCI soft core as the data communication core.In the process of software driver design,the portability of driver code is fully considered.According to the test requirements of different environments,the hardware-oriented driver and software application based on Windows system and VxWorks system and the system calibration based on AD chip self-calibration are designed respectively.The human-computer interaction interface is designed under Windows environment to realize the real-time control of the module.After completing the design of hardware circuit,firmware logic and software driver of the module,the module test environment is built,and the functions,parallelism indicators,synchronization indexes and dynamic indexes of the module are tested.The technical indicators of the test module meets the accuracy requirement,which verifies the feasibility of the design scheme and achieves the design expectations of the 32-channel parallel AD under the general test platform.
Keywords/Search Tags:CPCI, Parallel Data Acquisition, FPGA, Data caching
PDF Full Text Request
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