Design Methods For High-Throughput LDPC Decoder Arichitecture

Low-Density Parity-Check(LDPC) codes, which have Shannon limit approaching performance and support paralleled decoding, have been widely applied to various areas such as digital broadcasting, deep space communication and magnetic storage. In hardware implementations of LDPC decoders, especially those based on Field Programmable Gate Arrays(FPGA), it is difficult to realize decoders with high parallelism because of the structure of on-chip block memory, which limits the throughput of the LDPC decoders. According to the characteristics of on-chip block memory on FPGA, this dissertation aims at designing LDPC decoders with memory efficiency and high parallelism.Since LDPC decoders based on FPGA suffer from low parallelism introduced by on-chip memory of FPGA, a LDPC decoder architecture which is able to efficiently utilize on-chip memory of FPGA is presented. A designed decoder consists of several parallel decoding units. By rearranging the structure of memory, the decoding units are able to share on-chip block memory so that higher memory utilization rate is achieved. In this way, throughput of an LDPC decoder can be improved without occupying larger amount of on-chip block memory.Moreover, decoders for LDPC codes defined in Digital Terrestrial Multimedia Broadcasting(DTMB) and those in the Consultative Committee for Space Data Systems(CCSDS) are implemented with FPGA to validate the proposed decoder architecture. A hardware testing system is also implemented with FPGA to verify the presented decoders. The influences of quantization accuracy and number of iterations on performance are tested using this system.