Research And Realization Of LDPC Decoder In High Speed Data Transmission

In the last decade, because of its innate parallel decode algorithm and excellent error correction performance, Low-Density Parity-Check code(LDPC code) have been received close attention from numerous of investigator at home and broad. The coding and decoding algorithm of LDPC decoder and its hardware design and implementation are the focus of this thesis.In the first instance, the basic concept of the LDPC code and its coding and decoding algorithm is studied, and the Belief Propagation algorithm and the Min-Sum algorithm and its Modified Min-Sum algorithm is mainly discussed, then a new dynamic compensation decoding algorithm is presented. Secondly, the design of Quasi-Cyclic LDPC decoder is especially studied which is applied to high speed data transmission. In order to avoid or to ease off the access conflict of memories in the design of the decoder, the method of code transforming is adopted to converting the Quasi-Cyclic LDPC code into block Quasi-Cyclic LDPC code or similar block Quasi-Cyclic LDPC code. Simultaneously, a mothed for improving the throughput of decoder is proposed. In the last, optimizing and implementation of the function elements in the (8176, 7154) LDPC decoder is finished, including input and output control, variable node unit, check node unit and data storage, the throughput of the decoder can reach 800Mbps.