Research And Implementation Of JESD204B Receiving Interface Based On GTX

High-speed data acquisition systems play a very important role in applications of the wireless communication,medical imaging,high-speed instrumentation and radar system and so on.With the rising of ADC sampling rate,traditional parallel transmission technologies are exposing their weaknesses for reducing the difficulty of inter-code synchronization,inter symbol interference,routing complexity,and resource consumption.In this case,the high-speed serial transmission technology comes to the forefront.JESD204 B protocol is one promising candidate of high-speed serial transmission technology.Although large foreign companies provide commercial JESD204 B interface IP core,it is sold in high price.More importantly,the key parts of the IP core provided in a "black box" manner by the third-party,and users thus cannot understand the details.Employing these "black box" IP core in the field of defense industry will leave serious hidden danger to national security.Considering above problems,the implementation of JESD204 B receiving interface on FPGA is being explored in this thesis based on the study of its principles.Initially,the overall architecture is designed after the basic research of the structures and functions of JESD204 B receiving interface.The feasibility of implementing the physical layer of JESD204 B receiving interface using high-speed GTX transceivers is analyzed in detail.The implementation scheme of the link layer is designed and the mapping program between the data link layer and the user data is determined.Then the key problems of implementing the JESD204 B receiving interface as well as plausible solutions are analyzed.To verify the performances of the design results,the logic function and the timing performance of the designed JESD204 B receiving interface are simulated in Vivado and tested on the hardware circuit board.The simulated results demonstrate: 1)the logic functions of the realized JESD204 B receiving interface are accurate;2)timing analysis reports given by Vivado meet the frequency requirements.Board-level test results demonstrate that the functions of designed JESD204 B receiving interface are properly and stable.