Design Of Ultra-high Speed ADC For Coherent Optical Reciever

The booming of annual global IP traffic sets up more strict requirements for Optical Fiber Communication systems.Faced with the ever increasing IP traffic,advanced carriers,standardisation organizations,research institutions and vendors have been focusing on researching on the next generation optical transport network(OTN)related technology and standard.Coherent detect optical fiber communication technology,the key to achieving the goal of next generation OTN,can not survive without the ultra high speed data converters.Meanwhile,Ultra high speed analog to digital converters and digital to analog converters are considered to be the bottleneck of the circuit design in coherent system.However,there is still a huge gap between home and abroad of the development of the ultra high speed ADCs.In consciousness of the reality of domestic high speed ADC development and the severe requirements of ADC performances for future communication systems,a 4bit ultra-high speed ADC was designed in IBM 0.13um SiGe BiCMOS technology.With 4 channels Flash ADC work in parallel which speeds up the overall sampling rate of the final design,the Time Interleaving ADC becomes possible to meet the needs of coherent detect.The main contents included in this paper are list as follows.1.A systematic simulation and verification of the 16-quadrature-amplitude-modulation(16QAM)based coherent system was done with the help of OptiSystem and Matlab.The detailed introduction of the modules in the system is followed by a 4 Amplitude-Shift-Keying(4ASK)based 16QAM generation method analysis.As the very system which the ADC is applied to,systematic analysis comes out with a detailed performance requirements for the ADC circuit.2.Modeling and Simulaton of the time interleaving ADC system is carried out.Models for clock distribution circuit(CDC),track and hold amplifier(THA),4bit flash sub-ADC,and multiplexer are built in VerilogA or Verilog HDL.The verification of the theory of TI-ADC is a guidance for specific circuits design.3.A 4bit 15GS/s Flash ADC is designed and taped out.An analysis about the THA,Differential Reference Ladder(DRL),high speed comparator(CMP),Current Mode Logic(CML)encoder and multiplexer is made to understand the details of each circuit block.New balanced topologies of XOR and AND are adopted to meet the target of equal transmission delay from the two inputs to output.The whole area of the proposed ADC is 1050um×1890um and the total power consumption measured is 2.4W,measured sampling rate is up to 21.12GS/s.The measured DNL is-0.24LSB and+0.58LSB and INL is-0.13LSB and+0.58LSB.The measurement results show that the SINAD is 14.37dB with a 240MHz sinusoidal input at a 20GS/s sampling rate,and the ENOB is 2.1 bits.