System-level Power Modeling For Coarse-grained Reconfigurable Processor

Coarse-Grained Reconfigurable Architecture attracts the attention of academia and industry for its good compromise between program flexibility and energy efficiency.This paper focuses on the power consumption estimation of coarse-grained reconfigurable architectures in space exploration and builds a usable system-level power model for coarse-grained reconfigurable architectures.This paper explores the power modeling problem of coarse-grained reconfigurable processors from the architecture level,the circuit level and the process level respectively.The system-level power model that can be flexibly extended according to the architecture,circuit implementation and process nodes is proposed,which can consider the impact of power consumption early in the system design,to provide support for the design optimization of the coarse-grained reconfigurable architecture.Based on the composition of the coarse-grained reconfigurable architecture with classical static transmission and synchronization,we divide the sources of power into storage power consumption and non-storage power consumption,and establish parameterized architecture-level power consumption models respectively.Memory circuit which structure is regular,so the system structure parameters are clear.For nonstorage structure which are custom circuit,its internal structure are unknown.we use gate-level circuit simulation to obtain a single visit to energy consumption.Secondly,we modify the open-source power modeling tool-McPAT,based on the above architecture parameters.According to the existing coarse-grained reconfigurable architectures,the unmatched structure in McPAT is removed,the modules required are added,and the accuracy of the power consumption model of the newly added module is verified.Next,the statistical behavior of the program is run to provide performance statistics for the power input file.The number of cycles,the number of instructions,and the number of Processing Element are counted during the running of the program.Finally,the power consumption comparison experiment is designed,and the simulation results of the power consumption model are compared with those measured by the actual chip to verify the rationality of the power consumption model proposed in this paper.Experimental results show that when the coarse-grained reconfigurable processor contains only one PEA,the error between simulated power and measured power is-21.58%.With four PEAs,the error between simulated and measured power is-28.05%.This error exists because the model does not include:(1)inter-PE interconnect;(2)contextual memory.As a comparison,the power consumption simulation errors of the two references are-22.61% and-20.25%,respectively.However,after the model joins the modeling of interconnect and context memory,the simulation accuracy can be close to the above two power model.At the same time,with the current accuracy,the system-level power consumption model in this paper can support the design space exploration of CGRA.The results of this paper have been used in the follow-up research.