System Level Power Modeling And Optimization For Coarse-Grained Reconfigurable Architectures

Reconfigurable architectures are promising platform aim to get better performance than general-purpose processor(GPP)and higher flexibility than application specific integrated circuits(ASICs),thus become popular and widely used.Low-power design is one of the most important tasks in modern reconfigurable architecture design.Power-optimized modeling and design can be performed at the system level,software level,RTL level,logical level,component level and layout level.Optimizing at different level can lead to huge difference of the system power reduction range.If we have the power optimization on the system level,it will have a huge promotion on power optimization.Thus,has important practical significance.Therefore,this paper studies the system-level power modeling of reconfigurable systems and have the system-level power optimization.In this paper,faced to the power optimization of the coarse-grained reconfigurable architectures(CGRAs),we build an instruction look-up table focusing on the reconfigurable array power optimization analysis on system level and establish an improved instruction-level power model at the system level.Tested by the EEMBC benchmark,results show that the model has the error of 10% or less and it can guide the model through the power optimization.Based on this power model,we designed a power-aware task compilation algorithm based on the RSMap algorithm and optimized the power of the reconfigurable array at the instruction level.Based on the compilation algorithm,a LLVM-based GRVM compiler platform is designed to accomplish hardware compilation for coarse-grained reconfigurable system.By using the developed power-aware task compiler,the GREP reconfigurable architecture is tested in detail.Experiment shows our proposed approach could reduce the power consumption by 22.9% on average with only 3.9% decreasing performance.The results and methods have the great value for the design and application of low power reconfigurable architectures.