Design And Implementation Of Demodulation Technology For Telemetry Receiver Based On FPGA

With the development of wireless communication technology,the distance of communication is getting farther.As the key equipment for remote monitoring of measured objects,telemetry receiver has been widely used in many fields,such as unmanned aerial vehicle,launch vehicle,satellite and so on.The PCM/FM system has become the mainstream system in the field of telemetry because of its high precision.In this thesis,the demodulation algorithm and bit synchronization scheme of PCM/FM signal are designed and implemented on the platform of telemetry receiver based on PCM/FM system,and finally it achieves the expected target:When the telemetry receiver uses multiple symbol detection algorithm,the demodulation performance is improved by2dB at least compared with the frequency discrimination algorithm.Under the condition that the baseband symbol rate is 800kbps,the filter bandwidth in digital down conversion is 1.2MHz,and the BER is 10^-4,the Eb/N0 is lower than 9.5dB.In this thesis,the research background and demodulation technology of telemetering system are introduced firstly.For the PCM/FM signal,the theory and implementation process of signal modulation are expounded based on telemetry data acquisition transmitter at modulation terminal.At the demodulation terminal,the frequency discrimination algorithm and the theory of bit synchronization are introduced.Combined with engineering applications,the multiple symbol detection algorithm is used instead of the frequency discrimination algorithm to reduce the demodulation threshold.Aiming at the problem of high complexity,the baseband multiple symbol detection algorithm is improved,and a multiple symbol detection algorithm based on the screening process is designed.The algorithm uses the demodulated symbols to screen the number of local reference signals to reduce the complexity,and the algorithm is vertified by MATLAB.The lead-lag all digital phase locked loop is selected as bit synchronization scheme to provide the start position of symbol for multiple symbol detection module.Aiming at the problem that bit synchronization state can not be observed,according to the simulation results of phase detector and loop filter in phase locked loop,a bit synchronization state indication scheme is designed to visualize the bit synchronization status.Finally,in combination with the actual application requirements,the FPGA function is divided according to the above scheme,each module is designed and coded through the Vivado software.Matlab and Modelsim are used for simulation and test for function module,the correctness and feasibility of the whole demodulation scheme is proved.Telemetry data acquisition transmitter and telemetry receiver are used to build the test platform,and the overall scheme is tested for engineering.The test results show that the status of bit synchronization can be observed in the host computer,and the multiple symbol detection algorithm based on the screening process significantly reduces the required multiplier resources.According to the demodulation performance graph,the Eb/N0 of the telemetry receiver reaches 9.2dB where the BER is 10^-4.Compared with11.5dB of the result of frequency discrimination demodulation,the demodulation performace has increased by 2.3dB,which meets the requriements of the project.