Research On 3D Memory Built-In Self-Repair Technology And TSVs Fault-Tolerance

Three-dimensional integrated circuits refer to the use of through silicon vias(TSVs)as electrical connections to stack multiple homogeneous,heterogeneous chips or circuit modules in a vertical direction to perform one or more functions.Three-dimensional integrated circuits are considered to be a technology that goes beyond Moore's Law.Compared to two-dimensional integrated circuits,three-dimensional integrated circuits have many advantages: The interconnect length is shorter,the interconnect density is higher,the bandwidth is higher,heterogeneous integration is supported,the chip area is smaller,the storage capacity is larger,and so on.As a typical representative of highdensity integration of 3D integrated circuits,3D memory is one of the important application directions of 3D integrated circuits,but low yield is the major challenge to 3D memory.In addition,due to the immature manufacturing process of TSV,TSV is easy to introduce various defects in the process of manufacturing,thinning,alignment,binding,etc.,and failure to repair any layer in the manufacturing process will lead to failure of the entire stack.These conditions will further reduce the yield of the 3D memory.In order to solve the above problems,this paper aims to improve the ability of fault tolerance of 3D memory,we propose an efficient built-in self-repair(BISR)scheme to improve the fault cell repair rate of 3D memory.On the other hand,a cellular-based TSV redundancy architecture is proposed to improve the fault tolerance of TSV.The main contributions of this paper are as follows:(1)A three-dimensional memory built-in self-repair scheme based on row/column block mapping is proposed.The traditional memory repair scheme replaces the failed row or column with redundant rows or redundant columns.As long as one cell fails,the row/column of the corresponding storage array need to be replaced by an entire redundant row/column.The utilization of the redundant resources is not high,resulting in limited fault repair capability of the storage array.This paper proposes an effective threedimensional memory built-in self-repair scheme.This scheme first obtains the fault distribution of each layer of chips,and uses the proposed row/column block mapping algorithm to cluster faults of different layers.This fine-grained mapping can cluster as many faults as possible into the same rows or columns,which require fewer redundant resources to repair the same number of failures.Experimental results show that compared with other repair schemes,the proposed method has a higher repair rate and requires less redundant resources to achieve the same yield and the increased area overhead is almost negligible.(2)A novel honeycomb-based through silicon via(TSV)repair structure is proposed.Compared to the TSV arrangement of the rectangular structure,the honeycomb structure uses the same area to accommodate more TSVs,and the coupling capacitance and peak noise are smaller.Compared with other methods,the proposed architecture takes into account the balance between repair rate and hardware overhead,and achieves a relatively high repair rate with relatively little hardware overhead.The simulation results show that the proposed architecture has a repair rate of 99.84% for uniform faults,81.42% for high cluster faults,which has an average increase of 19.95% over the ring-based solution.The area overhead and total delay are reduced by 50.43% and 53.16%,respectively,relative to the route-based structure.