Fault-tolerant Design Of Through Silicon Vias Based On Diagonal Lines And Signal Delay

Traditional integrated circuits place various circuit components on the same substrate and transmit signals through metal interconnects.With the development of science and technology,the density of circuit elements on the substrate is increasing,which leads to the increased complexity of interconnect,increased power consumption,and other problems.The problems seriously restrict the development of integrated circuits.In order to improve the integration and performance of integrated circuits,the industry has focused on three-dimensional integrated circuit(3D ICs)technology.3D ICs,using through-silicon vias(TSVs)as signal transmission channels between adjacent layers,can increase integration density,shorten the interconnect length,reduce signal delay and power consumption,and integrate heterogeneous chips.However,since the manufacturing process of TSVs are not particularly perfect,it is inevitable that TSVs failures will occur,which can result in the failure of the entire 3D ICs.Therefore,in order to improve the yield of 3D ICs,it is necessary to design TSV fault-tolerant architecture.In this paper,the research works for the TSVs fault-tolerance architecture are as follows:1.This paper firstly presents a novel TSVs repair strategy based on diagonal redundancies.In the proposed strategy,redundant TSVs are arranged in diagonal line of TSVs block,and the whole TSVs block is divided into two disjoint sub-blocks.The repair path of TSVs is determined by redundancy repair algorithm based on maximum flow algorithm.Experimental results show that the yield of the proposed repair strategy is from 98.38%to 98.96%and the hardware overhead can be reduced by up to 70%compared to router-based technique.2.This paper proposes another TSVs fault-tolerance architecture based on signal delay for the TSVs faults uneven distribution and clustering distribution.The proposed scheme firstly divides functional TSVs into groups according to the fault probability and distance constraints.Then integer linear programming is used to allocate appropriate redundant TSVs for each group.The proposed fault-tolerance architecture not only satisfies the target yield constraint,it can also greatly reduce the signal delay.Experimental results show that the proposed scheme can reduce the signal delay by about 70%with little hardware overhead.