Design Of Microdisplay Driver Interface Based On MIPI Protocol

With the development of integrated circuit and information technology industry in recent years,consumer mobile devices have been widely used in our life.At the same time,due to the pursuit of display effects and portability,high-resolution microdisplays have been widely applied to electronic devices.However,with the increasing of resolution,the amount of data should be transmitted increases,which requires the inprovement of the transmission rate.In addition,it is required to maintain low power consumption and a small area.The traditional display interface has not met many requirements.To solve these problems showed above,a high-speed serial driver interface with the advantages of low power consumption and small area,has been adopted in this design,which is based on the MIPI(Mobile Industry Processor Interface)specification that apply to the high-resolution microdisplay.Firstly,this paper introduces the background,current situation of the research and the MIPI specification involved in the design.Secondly,this paper comes up with the system arch itecture of the interface circuit according to the requirements and the specification.The circuit consists of physical layer,application layer,low-level protocol layer and lane management layer.The interface supports a clock channel and 4 data channels,and the data channel supports transmission of image data in high-speed mode or transmission of control commands in low power mode.Thirdly,the Verilog HDL is used for the description of all modules,and a platform for verification has been built.In addition,the FPGA(Field-Programmable Gate Array)is applied for hardware verification,afterwards,the constraints are writed for synthesis,and the formal verification,netlist simulation,timing simulation and other verification methods are performed soon.At last,the chip is tested and analyzed,and its performance is improved.This design is synthesized with TSMC 55nm process by Design Compiler,and the area of circuit is 15426.32?m~2,with the highest working frequency of 900MHz.The innovations of this design are as follows.The system architecture is optimized,and the functions are simplified which are unnecessary for the design in the protocol.The state machine is simplified to avoid problems derived from jumps caused by the state machine being too long.The separation of the high-speed module and the low power module contributes to the clock management and the inprovement of the system stability.The reuse of ECC and CRC module will reduce the area and power consumption.The configuration module is designed to improve the flexibility and compatibility of the circuit.