Research On Calibration Technique Of Time-interleaved A/D Converter Based On FIR Filter

The high speed and high accuracy ADC has always been the ultimate pursuit of people.As the bridge of analog domain and digital domain,the high performance of ADC has been faced with many challenges.In the field of high-speed signal processing,technology and other factors has greatly restrict the sampling rate of ADC.People begin to explore the TIADC.The structure can multiply the sampling rate of ADC,so it has been widely used.However,each sub-channel has mismatch in the TIADC structure,which has a serious impact on the performance of the system.Therefore,accurate and efficient calibration of mismatch error in TIADC is important.With the improvement of the digital IC integration level,the digital background calibration technology of TIADC has become a research hotspot in academic and industry.This thesis describes the current development of the TIADC.Then analyze the main mismatch error of TIADC.First,the mismatch model is established.Then analysis the sub-channel mismatch(offset mismatch,gain mismatch,sampling time mismatch)of TIADC,a four channel TIADC digital background calibration algorithm based on LMS-FIR and interpolation filter is designed.The LMS algorithm converges rapidly,which can greatly reduce the performance loss caused by mismatch error.The performance of the algorithm is simulated through MATLAB platform.The sampling system input signal frequency is 12.55MHz,the system sampling frequency is 800MHz,and the sub-channel sampling frequency is 200MHz.Based on this model,the output signal before and after calibration is analyzed in frequency domain.we know that after calibration,the global noise of output signal is significantly reduced,and the performance is significantly improved,which SNR increased by 33.17dB,and the ENOB increased by 5.51bit.The algorithm is written in RTL and simulated by Modelsim.Before and after calibration,the SNR of the output signal is increased by 33.05dB,and the ENOB is increased by 5.49bit.Finally,use the SMIC 0.18 m 1P6M process to physical implementation.The area of Sequential unit and combinational logic unit after DC is 202117?m~2.The total area of the chip is about 3337293?m~2.The total power is 49.4964mW.The internal power consumption accounted for 92%,the switch power accounting for 8%.The static power consumption is only about 3.9597mW.After APR physical implementation,the chip size is510×510?m~2.Finally,the result of DRC/LVS prove the Logical correctness of the circuit.The PT result proves the Time series convergence of the circuit.