Design Of TIADC Mismatch Calibration Algorithm For Wide Bandwidth Input

With the improvement of semiconductor manufacturing process, the single-chip integration level on digital chipis higher, while the promotion in analog chip ADC performance is not obvious. Traditional ADC can't meet necessary needs, but still it is difficult to design high-speed and high-precision ADC. Now Time-interleaved Aanlog-to-Digital Converter(TIADC) achieves high speed by sampling with several ADCs at the same time, so it becomes a mainstream design of high-speed ADC.TIADC samples at high speedvia running multiple channels at the same time.However,the performance of systemis seriously affected due to the mismatch in manufacturing process. The paper analyzes three main mismatches existing between channels,proposing a calibration algorithm based on adaptive iteration for offset mismatch. The algorithm calibrates the mismatch by estimating the misalignment between the channels with the LMS iterative algorithm and calculating the difference between the to be calibrated-channel output and the reference channel output. As to gain and time mismatch of sampling, the paper proposes a calibration algorithm based on signal modulation. This algorithm exchanges the positions of main frequency and stray frequency with the basic principle of signal modulation to construct a coefficient, which equalizes the amplitude of after-modulated-main frequency energy and the amplitude of before-modulation-strayfrequency energy. This process eliminates the spurs introduced by the gain and time mismatch of sampling. By improving the differentiator in the algorithm, this algorithm calibrates input signal of wide bandwidth, which means the algorithm is not limited by input signal frequency.In order to verify function of the algorithm, a four-channel 12bits 200MHz TIADC model with three kinds of mismatches is built. When the normalized frequencies (fin/fs)of the input signal are 0.0197,0.32227 and 0.8019 respectively, the significant digits of output data can reach 11.65bits,11.69bits and 11.61 bits after calibration, which verifies the validity of the algorithm under different input bands. Then the paper designs RTL code with verilog for the algorithm, and verify the code function in Modelsim. Finally,the algorithm is verified in hardware with FPGA. At the same time, the algorithm is designed for ASIC process such as DC synthesis, formal verification, power analysis and automatic layout and routing.