The Design And Implementation Of Self-standard UHF RFID Digital Baseband Supporting IIC Bus Interface

With the rapid development of the requirements of Internet of Things?IoT?,Radio Frequency Identification?RFID?technology which is the front-end technology of IOT,has received extensive attention^[1].RFID is a kind of wireless communication technology that realizes information transfer and energy exchange between reader and tag by way of electromagnetic coupling through radio frequency signals.Among them,UHF RFID has the advantages of low price,long communication distance and fast data transmission speed,so that It is one of the key research directions of RFID technology.Inter-Integrated Circuit?IIC?is a multi-directional control bus that realizes simultaneous connection of multiple chips to the same bus,and each chip can serve as a control source for real-time data transmission.It simplifies the signal transmission bus interface,reduces space,the number of the chip's pin and interconnect costs^[2].Therefore,adding IIC interface to the digital baseband of the UHF RFID tag chip ensures that the chip can perform non-contact access through the RFID reader and other controllers can also access information in the chip through the IIC interface.It helps to expand the application of UHF RFID tag chip.The expansion.The main work of the paper includes:Firstly,on the basis of an in-depth analysis of the national RFID standard protocol Air interface for military radio frequency identification Part 1:800/900MHz parameters and IIC bus protocol,through the optimization of reducing the number of baseband work modules,a digital baseband architecture scheme that supports the IIC interface is proposed:the module of power management PMU,the module of initialization INIT,the module of dedode DECODER,the module of state jump SCU,the module of output control OCU,the module of memory interface IE,the module of IIC interface IIC_REP,the module of signal selection SIGNAL_SEL.And then gives detailed design methods for each module.Secondly,this paper focuses on low-power design methods and technical approaches for the digital baseband of the tag chip.Through comprehensive application of power management module,gated clock,calibration input multiple bits and other methods,the low-power design of the RTL level of the UHF RFID digital baseband supporting the IIC interface's autonomous standard is completed.Finally,based on the FPGA development board platform,the verification of the digital baseband of the tag chip is completed.The logic synthesis,timing verification,physical implementation and physical verification of the digital baseband were completed under the SMIC 180nm process.The verification results show that the completed digital baseband complies with all the functions specified in the agreement.The baseband area is90998.35?m² and the power consumption is 10.45?W.Comparing the digital baseband before optimization,the total power consumption was reduced by 18.4%while the chip area was increased by 6.1%,meeting the requirements of the design.