Tag Chip Design Of UHF RFID Chinese Standard Based On BLF

Passive UHF RFID (UHF RFID, Ultra High Frequency Radio FrequencyIdentification) tags with small size, large capacity, longevity, and can reused and so on,are widely used in logistics, identification, anti-counterfeiting, and high-speed charge.As RFID plays an increasingly important role in the development of information societyits standardization issues is becoming important, and China has brought forward UHFRFID Chinese Standard with independent intellectual property.A digital baseband design of UHF RFID tags based on Chinese Standard is givenin this paper. Firstly analysis of Chinese Standard was made, the data encoding mode,modulation mode, data rate and link timing in forward and backward link was presentedin great detail, and the security mechanisms in Chinese Standard were also introduced.The security of Chinese Standard improved comparing with the existing protocols.Since the power consumption determined the communication distance and the costprevents the large-scale application of RFID technology, so an new clock architecturewas brought forward to reduce the power consumption and the area. The new clockarchitecture was mainly about two aspects, firstly, BLF(Backscatter Link Frequency)was used as the main system clock; secondly, the command parse module and themodules related to the command parsing used the data synchronous clock from thedecoder module as the operating clock in the command parsing process. The digitalbaseband was divided into modules at first and then the design was completed based onthe new clock architecture, the work mainly consisting of RTL(Register Transfer Level)coding, functional simulation, synthesis, static timing analysis, power analysis, physicaldesign. The area and power of the design using BLF as the main system clock wasreduced by20%comparing with the design using2×BLF as the main system clock.The frequency dividing algorithm meeting the BLF frequency tolerance wasadopted. The automatic adjustment of frequency dividing coefficients lower theaccuracy requirements of the clock from the analog front-end. The implementation ofhalf integer dividing met the BLF frequency tolerance while reducing the hardware cost.Finally the chip was tape-out in TSMC using0.18μm low-power process. Aftertesting, the function and each indicator met the requirements of Chinese Standard.