100M Ethernet PHY Behavior Level Modeling Research

With the number of IC(Integrated Circuit)scale and complexity increasing,the increasingly fierce market competition,improve IC design ability,shorten the time to market to become the enterprise the key to success.In the traditional RTL(Register Transfer Level)there are many restrictions on chip research and development speed of digital IC front-end design process based on the problems in the.For example,the RTL designer document ambiguity in understanding the overall design problem can be found in the verification phase etc.However,based on the ESL(Electronic System Level)design theory can improve the development efficiency of the chip to a great extent,so as to shorten the time to market of chip.With the application background of 100BASE-TX Ethernet PHY(Physical Layer),this paper focuses on the research and application of 100BASE-TX Ethernet PHY behavior level modeling method based on the theory of ESL design methodology.The main achievements of this paper are as follows:From the transaction level modeling(TLM)point of view,a TLM modeling implementation scheme for a design circuit is proposed.The scheme divides the PHY main body of 100BASE-TX Ethernet into the transmission channel and the receiving channel,and abstracts the related functions of the circuit into different "methods".According to this scheme,the functions of each part of the circuit,especially the algorithms and principles of scrambling code and scrambling code,are deeply studied,and the design of the UML(Unified Modeling Language)view of each part of the circuit and the program idea is completed.Based on the UML view,the transaction level modeling of each part of the circuit is realized in System Verilog language.Guided by the ideas of TLM model communication refinement,adaptation and time sequence encapsulation,a scheme of behavioral level modeling for a design circuit is proposed.The scheme divides the 100BASE-TX Ethernet PHY into PCS(Physical Coding Sublayer)sublayer,PMA(Physical Medium Attachment)sublayer and PMD(Physical Media Dependant)sublayer.According to this scheme,the signal and time sequence of the design circuit are studied,and the behavior level model of each part of the circuit is realized by System Verilog language.Based on the UVM(Universal Verification Methodology)methodology,a UVM verification environment for RTL is implemented.This environment is completed before the detailed design of the RTL,and the reference model for the design in the environment is rewritten by the realized transaction level model.Then,based on the UVM verification environment,the simulation verification of RTL expansion unit level and integration level is fully utilized,and the coverage analysis work is carried out,and the verification requirements are achieved through analysis.In this paper,the transaction level modeling and behavior level modeling of the design circuit are treated,and the implementation model is used to verify the RTL.The practice proves that the ESL based design methodology has a significant advantage in the chip development.Statistics show that the model implemented in this paper provides 64 references and important support to RTL designers,which greatly improves RTL research and development efficiency.On the other hand,it is estimated that compared with the traditional design process,the project saves about 30% of the R & D time cost.In addition,the TLM model is used to check out some RTL errors which are difficult to detect by traditional verification methods.Through the research of this subject,it provides an important solution for the research on improving the design ability and efficiency of the integrated circuit.It provides a strong support for the theoretical research of the modeling methods of the behavioral category and the practice of engineering application,and makes some contributions to the research of the 100BASE-TX Ethernet PHY.