Behavioral profiling based high level power estimation methodologies for VLSI ASIC synthesis

Portable electronics and "hot" modern microprocessors are primary motivating factors for low power design of VLSI systems. Accurate power consumption estimation is necessary for any low power design tool. Power estimation methodologies at behavioral and Register-Transfer (RT) levels of design abstraction, implemented in a high level synthesis (HLS) framework, are presented. Average and peak power consumption of the design are estimated at the behavioral level. The methodologies exploit the profile data obtained by performing behavioral profiling of the input specification. Techniques for power characterization of datapath module library and PLAs are presented. Module library power characteristics and profile data are combined to estimate the power consumption of a given design. An RT-level simulation based methodology that exploits the hierarchical nature of the structural specification of the design, is presented. A simultaneous scheduling and operator binding algorithm to optimize power is also developed and validated. For each methodology, experimental results for benchmarks from an HLS benchmark suite are presented.