The Behavioral Level Design And Verification Of Mixed Signal Circuits

Consumer electronics, such as cellular phones, interactive televisions, media electronics, require analog/mixed signal (AMS) circuits in addition to major digital blocks. However, embedding AMS blocks in a system-on-a-chip pose a challenge to design and simulation, since it involves how to design and verify both digital and analog circuits at the same time. The presence of the mixed-signal hardware description language (MS-HDL) makes the behavioral description of mixed signal circuits feasibly.The analog circuit is the bottleneck for mixed signal circuits, so the research on behavioral models of analog circuits is the pivot of this thesis. Based on the research and the analysis of the analog hardware description language (AHDL) and mixed circuits behavioral level design methodologies, a behavioral level model of a charge pump phase locked loop (CPPLL), which is a typical mixed signal circuits, is designed. The behavioral level models of CPPLL include such sub modules: phase frequency detector (PFD), charge pump (CP), loop filter (LF), voltage control oscillator (OSC) and some auxiliary circuits. The design method of each module is modeling mathematic models firstly, and then using the mixed signal hardware description language to realize the module. Moreover, based on the analysis of the jitter types in PLL, the phase jitter and frequency jitter are added into the behavioral level models of PLL, which reflects the jitter feature in the behavioral level design and increases the precision of the behavioral level models.In order to implement the behavioral level verification of mixed signal circuits, a mixed signal system composed of 8 bits MCU and a charge pump phase locked loop is established in this thesis, then the system is verified, according to verification flow of mixed signal circuits. Moreover, the advantages of different description methods have been studied. The comparison of experimental results of CPPLL with behavioral level and transistor level description has been made. The experimental results show that the behavioral level verification has high efficiency compare with transistor level description verification.