100BASE-TX Ethernet PHY Chip Design And Verification

Since the advent of Ethernet technology in the late 1970 s,internet technology begins to develop rapidly and has been gradually penetrating into people's daily work and life.Fast Ethernet is the most widely used Ethernet technology on the terminal equipment in modern times.Ethernet Switch and PHY chips are almost exclusively monopolized by foreign companies,and the domestic traditional research on Ethernet almost focus on the data link layer or the higher layer.The research on the physical layer is relatively few,so this study makes a great contribution to the development of domestic autonomous Ethernet chips.Ethernet technology is composed mainly of two parts: medium access control(MAC)and physical layer(PHY).In this study,the design of digital circuit about the 100 M Ethernet physical layer based on the IEEE802.3 protocol has been completed,which meets the criterion well.The specific studies are as follows:The IEEE802.3 protocol of physical layer is studied,and the physical layer structure of 100BASE-TX is summarized.The working methods of PCS,PMA,and PMD and the functions of each sub layer are highly focused.And the circuit structure of the whole design and the logical relationship between the key signals are summarized.The related coding in each sublayer is studied.This study analyzed algorithms of various coding,scrambling codes and their implementation methods,and discussed characteristics of different coding methods,and then adopted suitable coding and algorithm for Ethernet physical layer.The differences between self-synchronizing scrambling code and synchronous scrambling code are contrasted by the method of list comprehension,which indicates that the synchronous scrambling should be adopted for the scrambling code of the 100 M Ethernet.The functions of specific modules on each sub layer are summarized,and also implemented by Verilog HDL language.To be specific,each sublayer is divided into specific modules according to the specific function.The realization methods of different modules are summarized according to the protocol,the flow direction of the data flow and the logical relationship of the control signals.Parts of the modules mainly use the state machine to realize the design,thus the state transition diagrams are summarized to elaborate the jump condition and the state jump,and then the RTL design is completed.The results of simulation and verification indicate the functions of the design are correct,and the synthesis report also indicates the design satisfies the demands of the timing constraints.After the design work,the verification platform is built to simulate and verify the design with the 35 verification items extracted according to the design specification,and the simulation results verify that the design satisfies the functional requirements.The functional coverage is 100%,and the code coverage rate of each module is above 95%.Furthermore,the DC synthesis tool is used to synthesize the codes,and the time sequence report shows that the redundancy time slack of the set-up time and hold time is respectively 0.06 ns and 0.14 ns.It is proved that the design satisfies the requirements of time sequence constraints.