Design And Implementation Of Testbench For Embedded Ethernet Controller Chip Based On UVM

With the continuous development of integrated circuit technology and the continuous improvement of manufacturing technology,the scale of chips has gradually expanded and the functions have become more and more complex.How to find as many as possible loopholes in the shortest time to ensure the completeness and efficiency of verification has become a key issue in the field of IC verification.At the same time,in order to meet the strong demand for chip verification,the verification language and verification methodology are constantly updated.The UVM verification methodology developed based on the System Verilog verification language has become the dominant player in the verification field today.This paper focus on the platform structure and core mechanism of UVM verification methodology.The communication methods of the UVM verification platform,verification mechanism,register model,and structural functions of verification components were analyzed in depth.It fully reflects the advantages of UVM verification methodology in terms of completeness,efficiency,reusability,and flexibility of the verification platform.In this paper,the embedded ethernet controller chip is used as the verification object,the working principles,the connection of each module and typical TCP/IP protocols of the embedded ethernet controlle chip are fully introduced and analyzed.According to the functions,scenes,interfaces,exceptions,registers and other dimensions of the embedded ethernet controller chip,the simulation function points are extracted.And established a hierarchical verification platform based on UVM.The verification platform integrates three sub-environments,scoreboard,register model,assertion,and functional coverage collection components.The design ideas of the UVM verification platform,the implementation of each component and the communication methods are described in detail.Based on the verification platform,testcases are written,and the verification results are analyzed in combination with simulation waveforms and simulation log.Finally,use VCS simulation tools to automatically collect code coverage and functional coverage.Analyze and explain the simulation points that cannot be covered.In the end,the goal of 100% functional coverage and code coverage over 90% was achieved.After the simulation is completed,the innovation of this paper is analyzed,and the shortcomings in the verification process are summarized.Practice has proved that the verification platform designed in this paper with clear hierarchy and structure,has high efficiency,completeness,flexibility,and reusability.At present,the chip has been successfully taped out,and some components have been successfully transplanted to other projects.