The Fdp Fpga Chip Programmable Logic Unit Modeling And Fault Test

FPGA(Field Programmable Gate Arrays)is a kind of widely used programmable device through the world, its appearance not only deeply shortens the design period of ASIC(Application Specific Integrated Circuits),reduces the huge cost of design, but also makes up the blank between the ASICs and CPLDs.This dissertation works on hardware modeling to the FDP-3 FPGA chip which designed by the Institute of Microelectronics of Fudan University by Verilog HDL language. The main method is to convert the CDL file to a Verilog file with a Perl program which is self-designed. Obviously this method can reduce the loading and mistake of manually modeling. The chip model could be simulated in software ModelSim, and through a instance the correctness of the chip model and the method of modeling can be justified.This paper also works on improve the fault detecting algorithm of the FDP-3’s configurable logic resources.Using 9 kinds of test configuration and relevant test vector make the Logic Cell tested completely, which is the minimal logic cell of FPGA.Through the software TurboFault, the test coverage could reach 100%.And based on the concern of the connecting between the Logic Cells of whole chip, these test configuration and relevant test vector could fully test logic cells in the chip theoretically.