The Implementation Of Video Acquisition And 3D Noise Reduction Based On FPGA

Video has the advantages of intuitive,reliable and rich content.with the development of automation technology,video processing technology is gradually used in geological mapping,security,mineral processing,crop growth and other fields.The presence of suspended solids in the atmosphere results in unclear video images,which not only affect the visual quality of human beings,but also have an incalculable effect on video post-processing.Therefore,video denoising is especially important.Traditional image processing is based on the software,however,it is difficult for software to meet the requirement of real-time when processing large amount of data.Because the hardware has the characteristics of parallel processing data,the hardware that based image processing technology is gradually concerned.FPGA has rich hardware logic resources and storage resources.Owing to convenient and flexible configuration,fast processing speed and easily transplanted,FPGA is widely used in real-time image processing field.In this paper,the FPGA technology is used to capture and reduce the noise of the video captured in the atmosphere environment with a large amount of suspended objects.This paper first introduces the development of image processing technology,and briefly analyzes the advantages of the video image processing technology based on FPGA,the traditional video image acquisition system and the classic video image noise reduction technology.Traditional video image acquisition system based on software platform,MCU and FPGA + ARM embedded system,and the classic video image noise reduction technology is based on spatial filtering,time-domain filtering airspace joint filter in time.Finally,the paper focuses on the basic principle and characteristics of the 3D noise reduction algorithm used in the video image.The algorithm has the following differences from the classical video denoising algorithm: Using the difference graph method instead of image block matching method to separate the image background and foreground,the key control threshold method is used to replace the signal variance threshold method to mark the noise signal.Then we introduce the video image acquisition and display system based on FPGA.When designing the system,it can be divided into four modules respectively by adopting the idea of modularization: video coding and video decoding chip initialization module,digital video and effective data acquisition module,SDRAM controller module and video data display module.This article focuses on the logic design of the chip initialization module and the SDRAM controller module.The chip initialization module is the prerequisite for video data acquisition and display.This article configures parameters through the I2 C bus,and focuses on the FPGA implementation of the I2 C bus controller.The SDRAM controller module is one of the difficulties in the design of this paper.It is the bridge between the FPGA chip and the off-chip memory for data transmission.In designing this module,two asynchronous FIFOs are used to cache the data written to the memory and the data read from the memory,respectively,to improve the versatility of the controller.Finally is introduced in this paper,the design of 3D video image noise reduction system based on FPGA.The system with Altera corporation FPGA chip as the core,composed of peripheral interface circuit,image noise reduction processing circuit and control circuit composition.These circuits are on the same FPGA chip design implementation,so the system is simple and reliable.Among them,the control circuit of peripheral equipment completed by FPGA chip is: SAA7113 chip initialization,SAA7121 chip initialization,SDRAM controller and data interface cache.The I2 C bus controller is designed to complete the chip initialization;design and off chip memory SDRAM controller to control the FPGA chip;design the data transmission between the cache data interface circuit to solve the problem of data across the clock domain.Among them,the high-pass filter circuit is used to mark the noise signal in video image,and the initial noise map of video image is obtained.The edge detection circuit is used to modify the initial noise map and get more accurate noise map.The data differential operation circuit is used to extract the image foreground in video sequence.Median filter circuit is used to filter the noise signal in foreground.The control circuit of FPGA chip has global control circuit,which is used to control the data access of the system.In order to improve the working frequency of the system clock,the fast median filtering is realized by using the flow technology in video noise reduction algorithm.In order to reduction algorithm,image difference image method is used to replace image block matching method to separate video image foreground and background.The experimental results show that the video image processing system designed in this paper satisfies the real-time processing requirements of video image.