Algorithm Research And Hardware Implementation Of Digital Video Noise Reduction

In the digital video image processing system, digital video capture、encoding、transmission and decoding process will introduce all kinds of noise inevitably. Thepresence of noise not only affects the subjective visual quality of the video seriously,but also affects the digital video processing, such as brightness enhancement、imagescaling、2D to3D and other processes. Therefore, with the extensive application ofdigital video, digital video noise reduction technology is important particularly.Digital video noise reduction technology will not only be able to filter out noise in thevideo, improve video subjective visual quality, but also plays an important role forvideo processing tasks, such as video compression、frame rate and object recognition,etc.In this paper, the existing digital video noise reduction algorithms are studied, theadvantages and disadvantages of each method are analysised and then a new digitalvideo noise reduction algorithm is proposed on the basis of extracting the advantagesof all methods.Firstly, carrying out motion detection between the current frame and the referenceframe of the two frame images. As the accuracy of motion detection video noisereduction process has a vital role on the whole, affecting the quality of video imageprocessing directly. So this paper selects to use occupying larger FPGA hardwareresources but operating simple relatively motion estimation method which is based onblock matching to ensure the accuracy of image motion detection.Then doing intensity of the image motion estimation, setting a threshold value todetermine whether to perform spatial domain filtering or temporal domain filtering.The threshold value will be changed according to the size of the noise estimate valueadaptively. The temporal domain uses the classical weighted average filter to filter outnoise in the video image. It has been improved on the basis of the original algorithm.Spatial domain filter applies fast median filtering algorithm. Finally, doing the hardware implementation and verification of this algorithm. Inthis paper, the whole design of the hardware architecture is divided into severalsub-modules. In order to view data processing errors conveniently, each module hasits own input ports and output ports. This is easy to implement pipelining.The algorithm proposed in this paper combines the advantages of the existingexcellent algorithms. So it can suppress the noise in the video image and protect theimage details in effect, avoid obvious visual degradation, such as blockiness.Simultaneously, this can meet the requirements of saving FPGA hardware resources,saving space and reducing cost.