Research Of High Performance Fractional-N Analog PLL

The function of phase-locked loop is to track a special system with another system.In other words,it is a circuit that the output signal of oscillator is used to track reference signal,and finally make them equal in phase and frequency.It is widely used in frequency synthesizer,clock and data recovery(CDR)and high-performance digital circuits.With the decreasing size of CMOS process and the decreasing of supply voltage,the characteristics of low voltage,high frequency,low phase noise and fast locking are becoming the research direction of phase-locked loop.At the same time,the fractional frequency phase-locked loop can overcome the limitation of integer frequency phase-locked loop,so it is widely used.The phase-locked loop circuit researched in this paper is mainly used in frequency synthesizer.First,the basic principle and system composition of phase-locked loop are introduced,and the working mode and performance index of each module in PLL are introduced.Next,from the perspective of system,under the condition of loop locking,the phase-locked loop can be regarded as a linear negative feedback system,and the stability and dynamic characteristics of the loop in the S domain are analyzed.Bring the transmission function of each module into the system,according to the maximum phase margin value,the value of resistances and capacitances in the filter can be calculated.Then we deduce the phase noise transfer function from the noise source to the output end of the loop,and get the transmission function of the phase noise of each module,in order to guide the selection of the system index.After the system analysis,this paper designs and optimizes each module with SMIC 0.18μm CMOS technology.The state machine structure with digital trigger is used in PFD circuit.A switch-controlled delay chain is added to select the delay time and to eliminate the dead zones.The CP circuit adopts the Operational amplifier to reduce the nonlinearity.At the same time,a programmable current mirror is used to change the value of the current,and adjusting the loop bandwidth.The three-order structure is used in the filter to suppress the high frequency noise.The VCO of LC structure with 16 capacitances can achieve wide band tuning range and low phase noise.The high-speed two frequency division structure is used into the divider to produce the orthogonal I/Q signal,and the MASH 1-1-1 structure is used to realize fractional frequency division function.A phase-locked loop circuit for frequency synthesizer is designed in this paper.It is designed by SMIC 0.18μm process,and the supply voltage is 1.8V.The input reference frequency is 40 MHz,and the frequency range is from 4.85 GHz to 5.35 GHz.Through high-speed two frequency divider,we can get orthogonal I/Q output frequency from 2.43 GHz to 2.71 GHz.When the output frequency is 5.12 GHz,the lock time of phase-locked loop is less than 65μs,and the phase noise is-119.02 d Bc/Hz at 1MHz.The performance of simulation meets the requirements of IEEE802.11a/b communication protocol for frequency synthesizer.