Design And Implenmentation Of Rader Processing Engine Based On VLIW Structure

Radar signal processor as an important component of the radar system which is used to realize real-time processing of radar received data directly affects the performance of the radar.With the development of integrated circuits,the signal processing system of radar systems is also continuing to be digitalized.Both the scenes and the algorithms of radar applications are becoming more and more flexibly and it is hoped that the radar signal processing engine can have configurable features and can be flexibly adapted the different requirements.The commonly used ASIC implementation methods have a long design cycle and poor flexibility,DSP implementation is not specific enough,can not achieve the same performance of ASIC implementation methods.How to take into account both specificity and flexibility during the design of radar signal processing engine is the new challenge.The thesis is based on a radar signal processor project of the national ministry.Facing to the requirement of real-time processing of radar signals in PD?pulsed doppler?radar,an application specific instruction set processor?ASIP?for signal processing of PD radar is proposed as the radar signal processing engine.In the thesis,a set of dedicated instruction is proposed to flexibly adapt to the different radar signal processing requirements in various scenarios through programming.At the same time,by anazlying the features of radar signal algorithms,we design special structure and application specific instructions to meet the real-time requirement.In this thesis,the special structure and instruction design of the ASIP for PD radar signal processing are mainly studied.The principle of the key radar signal processing algorithms is studied,and the parallel scheme of the core algorithms is explored.The detailed work are belows.We extrat the feature of radar signal processing algorithms with lance and gnu tools,locate hot spots in the algorithm source code,extract basic operations,and design special instructions to perform hardware acceleration.In the implementation process,the Harvard architecture and the 5-stage pipeline are used.The number of VLIW channels is 5and the SIMD width is 64 bits.To realize collision-free access,multi-bank memory and optimized address mapping methods are used.For a large number of loops in the algorithm,a dedicated hardware loop fetch unit is designed.To solve the problem of data correlations within and between VLIW channels,a dedicated data bypass network unit is designed.Finally,the verification is completed in two aspects:structural verification and system verification.The loop core code of FIR and FFT operations is encapsulated into the form of function.Comparing the hardware result with the matlab result,the relative error is in the order of10^-3.The proposed design is synthesized in ISE targeting at Zynq7020.The internal frequency could reach at 182.774Mhz,which meets the real-time processing requirements of the scenario in the paper.At the same time,through programming,signal processing algorithms can be upgraded and updated,reflecting the flexibility of the radar signal processing engine designed in this paper.Comparing with TI C64 processors on the market,the speedup of our design performing FIR and FFT with the same points can reach 2 to 3times and 5 to 6 times respectively,reflecting the specificity of the radar signal processing engine.