Research On Implemention Of Complex Digital Signal Processing Algorithm

In the application of complex digital signal processing, the traditional digital signal processor (DSP) can not meet the requirements of real-time and flexibility. Application Specific Instruction Set Processor (ASIP), which is based on Instruction Set Architecture (ISA) and is a branch of ASIC, combines the high processing speed performance of ASIC and the programmability of DSP. In recent years, ASIP is becoming a new study field of hardware realization. Especially, parallel architecture of ASIP can achieve a design with high parallelism and complexity. And ASIP also has good scalability, it can designs a specific functional unit, which makes the ASIP achieve the design with higher parallelism and higher complexity. This paper contains the following three parts of work focusing on the design and the application of the parallel architecture of ASIP and functional unit of ASIP:First, the typical ASIP parallel structrures based on the Reduced Instruction Set Computer (RISC) are introduced: SIMD structure, MIMD structure and tight coupling structure. And a SIMD structure with guarded instruction is designed and implemented in this paper.Second, the SIMD structure of ASIP is used to achieve 1024 points FFT based on Xilinx FPGA Virtex5 LX85.Third, the adaptive binary arithmetic coding is implemented with the structure of hardware state machine controlling pipline. And we taking this design for an example, the thought of taking hardware state machine as a specific functional unit of ASIP is illustrated.