Research On Vectorization Technology For Multi-cluster And VLIW DSP

BWDSP is a high-performance digital signal processor(DSP) with Very Long Instruction Word(VLIW) and Single Instruction Multiple Data(SIMD) architecture. Compared with general-purpose processors, VLIW processors give new challenges to complier for instruction is scheduled by compiler instead of hardware in VLIW processor. What’s more, BWDSP provides a large number of special instructions which can not be generated by general compiler.The main work of this paper is to redirect Open64to the target architecture BWDSP, and then on this basis we give two vectorization algorithms that one bases on storage location and the other bases on tree matching. At last, we give a special instructions synthesis algorithm framework.In vectorization algorithm based on the storage location, the front-end uses pragma to help identifing the loop which could be vectorized. After pre-handle and code motion, the algorithm synthesises the vectorization instruction. Then the algorithm call the modified clustering algorithm and register allocation algorithm for the loop, and insert the inter-cluster transfer instructions into the chain of the instructions if need. The experiment results show that the algorithm has great performance improvement for computing intensive program.Due to the structured hierarchy characteristic of the intermediate representation, whirl, the vectorization algorithm based on the tree matching changed the whirl tree during the whirl-lower from high whirl to mid whirl. The steps of this algorithm include pre-analysis, special vectorization handle, pre-handle, SIMD instructions synthesis, SIMD reduction and follow-up processing.At the last of this paper, we describe a algorithm framework for synthesising the special instructions. The algorithm models for the special instructiongs first, and then analyse the feature of the special instruction in the whirl tree. During the whirl-lower processing, the algorithm finds out the right match of the special instruction in the whirl tree and replace the whirl node with a new one which stands for the special instructions. Also, we must add the information of the special instructions in the machine description for the code generator to generate the special instructions. The algorithm framework get preliminary validation when we use it for the systhesising the MIN instruction and MAX instruction.