The Design Of On-chip Hierarchical Dynamic Scheduling Scheme For Heterogeneous Cluster-based VLIW Processor

Digital Signal Processor(DSP)is usually designed dedicatedly with the features for the oriented application.The DSP based on VLIW architecture can execute the sub instruction segments or instruction domains in parallel,helping to reduce the runtime cost of continuous fetching and strengthen the computing performance.However,for heterogeneous function units configuration in the clusters,the imbalance of computing and memory resource caused limited real time performance,which needs to be improved.In this work,we proposed an on-chip hierarchical dynamic scheduling scheme based on the technique knowledge about the typical dynamic scheduling and VLIW instruction scheduling and the features of the heterogeneous cluster-based VLIW DSP.With the intra-cluster and intercluster scheduling scheme,the dynamic scheduling for computing and memory resource was designed by dedicated registers setting,instruction packaged dispatching,dedicated latency with function specification,instruction dependency checking and intra bus selection.Besides,the prefetching and buffering scheme for loop execution was added for the low power optimizationThe experiments were implemented with the standard EDA tools for function simulation,logic synthesis and power estimation.With the typical digital signal processing algorithm mapping,the computing and hardware implementation performance was evaluated based on three different function unit configurations for the VLIW processor design.According to the experiment data,the on-chip hierarchical dynamic scheme can help the system get the improvement of computing performance up to 12.41%,with the overhead in about 5% and the coverage power increase in only 1.32%.