Simulation And Experiment Of Radiation Effect Of CMOS/SOI Devices And Circuits

Silicon-on-insulator (SOI) technologies have been developed for radiation hardened military and space applications. Many efforts have been made to very high levels of radiation hardness have been achieved. The total dose, single-event effects of SOI devices were studied in this thesis.We have investigated the mechanisms of single event effect for SOI device and erected the 1-D model of SEU ( Single Event Upset) for SPICE. MEDICI were used to discuss the SEU caused by all kinds of the ions strike. The results of simulation are consistent with the model of charging funnel. A CMOS device design technique based on SOI process,using actively biased isolated wells for single event upset hardening,has been described. HSPICE simulations were performed to simulate inverter constructed by actively biased isolated wells.10 keV X-ray test were performed to study Total-dose irradiation effect of partially-depleted CMOS/SOI transistors with gate-all-around structures fabricated on standard SIMOX and improved SIMOX. It is confirmed that for the back gate of gate-all-around, PG is the worst case; for the top gate, ON is the worst case.And the CMOS/SOI fabricated on improved SIMOX has better performance of radiation hard.We have taken the lead in investigating the mechanism of Total Dose effect for NMOS/SOI and a 2-D MEDICI model was erected,which could used to simulation Total Dose effect of different structure SOI device. And discussed how to improve the irradiation hardness capability for SOI devices and circuits.