Research Of SOI-MOSFET Model Based On BSIMSOI

With the development of technology,the feature size of the device(mainly refers to the gate length of MOSFET)is reduced to less than 100nm,especially under 22 nm,and the bulk silicon CMOS technology has met the bottleneck.The process of bulk silicon has not been able to move forward complying with the law of Moore.It has many influence factors,such as the short channel effect,the increase of the leakage current of Source-Bulk,Drain-Bulk diode and so on.SOI makes up for the defects and shortcomings of thebulk silicon in its full dielectric isolation technology.Compared with the bulk silicon CMOS,the change of SOI on the structural is not great,people can use the same manufacturing equipment and technology as bulk silicon CMOS.However,it is also necessary to make effective use of the subtle changes of SOI.Even the most simple integrated circuit design is also starting from the circuit simulation,thus the accuracy of the modelis particularly important.The previously reported models have mostly focused on a single fixed size,which are usually based on the Berkeley short channel insulated gate field effect transistor and thencombine a radio frequency parasitic subcircuit.Due to the lack of proper RF scalable model,the available size of deviceis limited for the RF IC Design Engineer.Or perhaps engineers need a fairly large amount of modeling efforts.Therefore,the study of RF scalable model is especially important.Although there have been some engineers did some research on the scaling rules,the physical meaning of the scaling equation is not clear.The rules are basically numerical analysis or pure mathematical expressions,which can lead to some unexpected problems,such as negative resistance or negative capacitance,in certain size points.In view of this,a RF scalable model based on physical layout structure is needed to be studied.In this thesis,the BSIMSOI(Berkeley Short-channel IGFET Model SOI)model parameters have been extracted from the 0.13um TB MOSFETs(offered by the Grace Manufacturing Company)of a Research Institute.Eventually make the current-voltage(IV)and capacitance-voltage(CV)characteristic curve within the coverage range of sizes to achieve a better fitting precision,and the errors are controlled within 5%.Next,use this DC model as core model to analyze the radio frequency parasitic of this batch of transistor.A newdevice structure with the drain shorted to the source is produced for extracting parasitic substrate.Studyingthe relation between the substrate parasitic and size scaling based on practical process and extracted parasitic parameters to map to other size of transisor.Then,study the remainingRF parasitic based on the layout structure,mainly the calculation formula of RF parasitic resistances and capacitances to preliminary determine the proportional relation between the parasitic components and the device size.Finally,combined with the RF small signal equivalent transistor topology,use analytic parameter extraction methord to extract parasitic and optimize these parameters based on test data under different operating bias(S parameter:scattering parameters)to obtain the relationship between the parasitic parameters and the size of the device.And then,establish the final scalable equations of RF parasitic.It can not only good to avoid the problem mentioned abovehuge amount of work and can also ensure the scalable accuracy.Since this initial establishment of scalable equation is the physical layout structure as a referenceand is similar with the trend of parameter extraction and optimized result,it greatly shortens the modeling cycle.