| With the continuing scaling of critical dimension and innovation of IC processing, technological advances in MOSFET has significantly improved the performance of devices and the computing capacity of chips. However, a series of proximity effects which result from elaborate layout cause the performance fluctuation of nano-scale devices, bringing random error and reliability concerns to the very large scale integrated circuit. The lack of MOSFET device model which covers layout proximity effects in China caused the difficulty to describe proximity problems precisely. Therefore, it is with considerable value to set up MOSFET model which can accurately describe the electrical behavior of the devices under these layout proximity effects.The mechanism analysis of layout proximity problems in this paper consist of four parts:sub-wavelength lithography, stress engineering, high-energy ion implantation and transient enhanced diffusion effect. The performance fluctuation of nano-scale devices under these effects is embodied in the threshold voltage Vth and related currents. As a consequence, BSIM4.5 model which is threshold voltage based has been chosen to set up the whole layout proximity model. This paper accomplished 130 NMOS devices and PMOS devices in different sizes based on domestic 40nm 1.1V Low Power MOSFET process, and completed parameter extraction on the strength of BSIM4.5 in the aspect of C-V model and I-V model. The average error of MOSFET core model which has extracted is less than 2%, and the error of standard deviation sigma is less than 5%, both of which meet the industry standards.Because BSIM 4.5 model is incomprehensive in the aspect of layout proximity factor, on the basis of MOSFET core model, according to different mechanisms, there are four kinds of layout-related factors involved into layout proximity model research including STI stress proximity factor, well-proximity factor, active-proximity factor and gate-proximity factor in this paper. Four micro models have been set up against different proximity factors. Micro models in this paper takes 11 factors in to account to cover above-mentioned layout-related effects, adding 28 model parameters to describe them as well such as KSODXU0 and KSODXVTH0. Micro models have been added to MOSFET core model by modifying threshold voltage expression Ⅴth and mobility expression μeff to accomplish the whole layout proximity effects model.With 392 test structures including NMOS and PMOS which are designed for model verification, the layout proximity model can effectively cover big size, short channel, narrow channel and small size devices, predicting MOSFET threshold voltage change up to 1-11mV and drain current change up to 0.5%-4.5% according to different proximity problems. The layout proximity effects model can effectively decrease the simulation error in IC design.40nm MOSFET layout proximity model implemented in this paper can correctly describe MOSFET’s electrical behavior in 40nm IC process and performance fluctuation under layout proximity effects. With high readability and portability, the model can be used for processing description and circuit simulation. This promotes China’s industrialization application of building device model independently. |
