| In this paper, based on the physical mechanisms of hot-carrier degradation of small dimensional MOSFET , the MOSFET characteristics degradation induced by the hot-carrier effect are deeply studied analytically and experimentally, The method to predict the lifetime of devices and circuits is given and MOS digital and analog circuit structures for the resistance of hot-carrier degradation are presented.First, the scaling limitation and relative reliability problems are analyzed for MOSFET in VLSI, especially for hot-carrier effects of small dimension MOSFET. And a review of the study of hot-carrier effects on devices and circuits is presented.Account for the high electrical field induced from the high applied voltage relative to small dimension device, the mechanism of hot-carrier generation is analysed, the Si-H bond broken model for hot-carrier injection and interface states generation is deduced and the substrate current model is developed. Also, the degradations of n-MOSFET and p-MOSFET are compared and the increase of delay-time induced by device degradation is represented by introducing "time-index", and the saturation effect and temperature characteristics of device degradation are described.Considering the unsymmetrical distribution of interface states induced by hot-carrier effects along the channel, the quasi-two-dimensional analysis methods are used to deduced the drain current, threshold voltage and electrical field in channel after hot-carrier degradation and the theoretical results are fully verified with the experimental data and M1NTMOS6.0 simulation output. The degradations of device output conductance, subthreshold conduction and RF characteristics are also analyzed.In order to investigate the effect of high-field hot-carrier on devices andcircuits, the electrical stress experiment is carried out with 1.2 n m, 1.0 n m and 0.8u m channel length home-made MOSFET's by the monitor system with ATE andCAT technology. By using the fresh and degraded experiment data, BSIM2 modelparameters are extracted.The degradation and lifetime model is deeply discussed, dynamic and staticstress suffered by devices and circuits are compared and analyzed. A modified model for Lc is proposed for better fitting the experimental data and thesubstrate current model parameters Eerit and Lc , degradation parameter H, m,nare extracted by the static stress experiment results. Also, the principle of CAS module of the reliability simulator BERT 2.0 is given and a 11 stage ring oscillator is used as an example for BERT to predict the lifetime of devices and circuits. The electron radiation experiment for MOSFET's is done with general linear accelerator and the simple method to predict the device lifetime by the electron radiation experiment is given.Finally, according to the MOSFET's parameter degradation due to hot-carrier effects and different application environment of MOS devices on analog and digital circuits, the circuit structures for hot-carrier immunity are proposed for digital applications by adding a Schottky diode in series with the drain of the nMOSFET suffered heavily from hot-carrier degradation., and for analog applications by adding a normally-on nMOSFET in series with the n-MOSFET in an analog circuit respectively. According to SPICE3f5 and BERT2.0 simulation results, the substrate current of new structure CMOS inverter is suppressed to about 50% of its original value and good hot-carriers resistant behaviors are obtained without adding any extra delay. Also, by using the hot-carrier immiunity analog circuit structure, the output resistance degradation caused by the hot-carrier degradation is deeply supressed and the small-dimensional effect can be improved shown by the SPICE 3f5 simulation results, and the gain degradation of a CMOS operation amplifer after 10 years operation decreases from 23% to 10% with this structure according to BERT2.0 simulation. Therefore, the solution to the hot-carrier degradation of MOS circuits is obtained. The other hot-carrier immunity te...
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