Research On Novel Structure And Analytical Model Of Low Loss Power MOSFET

Power semiconductor devices served as the critical components of power management systems have been widely used in consumer,healthcare,transportation,and aerospace sectors.Power semiconductor devices play a more and more important role in human daily life and economic development.Since 1950s,with the replacement of vacuum tubes by solid-state devices,we have ushered in a new industrial revolution.Most importantly,the emerge of MOS gate control technology provides an opportunity for the development of power semiconductor devices.Power MOSFET based on this technology has received increasing attention from researchers.Up to now,power MOSFET still occupies an important place in semiconductor market,and continues to grow up with the renewal of fabrication and design concepts.However,limited by the inherent shortcoming of physical construction,power MOSFET still shows higher power loss,which cannot meet urgent needs for the miniaturization,intellectualization,and energy conservation of power systems.This dissertation focuses on the reduction of power loss in power MOSFETs.Novel low loss power MOSFET structures,charge division,energy band modulation,analytical C_GD and“silicon limit”model,and edge termination optimizations will be studied.The relevant problems are discussed in detail through theoretical analysis,TCAD simulation,and experimental fabrication,which are described as follows:(1)Mechanisms of charge division and energy band modulation and analytical model of parasitic capacitance.Starting from the depletion of ionized impurity charge in drift region during the switching of 25 V low voltage power MOSFET devices,charge division mechanism has been established,which indicates that the charges electrically coupled to gate and other positions are equal to total ionized impurities of drift region.Therefore,charge electrically coupled to gate(Q_GD)determines parasitic C_GD,and switching loss can be reduced greatly by controlling charge division.Based on this,shield layer(SL)structure is proposed and an analytical C_GD model is established.In addition,the SL structure introduces energy band modulation to reduce length and doping concentration of channel region.Therefore,on-resistance(R_ON)and C_GS can be also improved.Due to charge division and energy band modulation of the SL,the novel device shows improved R_ON×Q_G,which is 35.5%smaller than the conventional MOSFET.(2)Narrow gate(NG)low loss power MOSFET device.In conventional 25 V low voltage MOSFET structure,C_GD can be reduced by separating whole gate polysilicon into gate and ground FP,however this also adversely introduces parasitic gate-plate and drain-plate capacitances.NG structure can be built by deposition of a thin polysilicon layer and etching step to remove the middle portion of whole gate polysilicon,thereby reducing C_GS from the view of physical structure.Moreover,a low-k dielectric layer can be formed below the NG to reduce C_GS further.The experiments show that the width of NG is less than 100 nm and the NG device achieves R_ON×Q_G of 34.1 m??n C,which is about 11.6%smaller than the conventional device.In addition,by studying electric field crowding and parasitic npn-BJT punch through in transition region of edge termination structure,the deterioration of breakdown characteristic has been successfully removed.Finally,the feasibility of applying NG to 80 V power MOSFET is analyzed and discussed.(3)Low loss lateral double-diffused MOSFET(LDMOS)and analytical R_ON,SP-V_B“silicon limit”model.Aiming at the large power loss of conventional 700 V high voltage(HV)LDMOS,it is found that the essence lies in“silicon limit”,which means there is a power exponential relationship between R_ON,SP and V_B.Therefore,R_ON,SP of HV LDMOS increase sharply with the improvement of V_B.Then,the low loss TRN-LDMOS has been proposed,which features a high-doped n-type top layer on surface of drift region to improve current capacity.As for early breakdown in 3-D edge termination structure,charge imbalance and curvature effect are completely eliminated by optimizing transition region.Finally,a new analytical R_ON,SP-V_B“silicon limit”model of the TRN-LDMOS has been developed,which can be given as R_ON,SP=5.93?10^-6?22(T/298)^1.7?V_B²,where parameter?is equal to conventional triple RESURF technology,however parameter?shows 31.2%improvement.The low loss TRN-LDMOS achieves R_ON,SP of 86.49m??cm² and V_B of 805 V,which shows leading performance in existing 700 V application field.