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Design Of Data Interface For VLSI Image Processing System Based On FPGA

Posted on:2019-04-21Degree:MasterType:Thesis
Country:ChinaCandidate:X T QiFull Text:PDF
GTID:2428330572456315Subject:Engineering
Abstract/Summary:PDF Full Text Request
In the field of image processing,the parallel capability of FPGAs is often used to achieve rapid processing of large-scale images.However,in the uploading of image data,if the peripheral interfaces on the FPGA,such as network ports and optical fibers,are used,special IP cores need to be introduced.Taking up a large amount of on-chip resources of FPGA,if using the upper computer to transmit to the FPGA through the USB interface,it is not convenient for on-site debugging and testing.Therefore,how to achieve rapid uploading of large-size images has become one of the problems to be solved in this type of project.This topic uses the U disk to support the characteristics of large-capacity storage,high-speed data transmission,proposed a method to reduce FPGA overhead using ARM + FPGA architecture to achieve rapid read U disk large-size image data.This solution greatly improves the overall portability,integration,and ease of use of the system,resulting in more stable operation.The main workflow of this interface is: First,the device mapping of FPGA under Linux is completed by ARM,and its drive and read/write interrupt control are realized.Then FPGA sends an interrupt request to ARM,ARM responds to the interrupt request,and reads from U disk.The image files to be processed are processed by slicing and transferring to the FPGA by means of asynchronous parallel technology.Finally,the FPGA-based receive buffer management system transfers the images correctly to the subsequent image processing unit,thereby realizing the cross-platform automatic transmission function of large-size images.After testing,the interface can correctly transmit the image to the image processing unit within the time required by the system.Compared with the traditional MCU+FLASH implementation scheme,the transmission speed is increased by more than twice,reaching 2 Mbyte/s.
Keywords/Search Tags:ARM, Driver, Data Cache, FPGA
PDF Full Text Request
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