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Design And Implementation Of High Speed Data Recorder Based On FPGA

Posted on:2014-11-23Degree:MasterType:Thesis
Country:ChinaCandidate:J Y ShenFull Text:PDF
GTID:2268330422463233Subject:Circuits and Systems
Abstract/Summary:PDF Full Text Request
As the rapid development of human productivity and science, the data acquisitionhas become an important part of the modern engineering science. That acquire data anduse the result of analysis to guide human production and practice has been regarded as asignificant method. Modern data acquisition system is generally based on the embeddedchip platform. This paper focuses on a data acquisition system based on FPGA. Thissystem can acquire multiple analog signals, then process and store the acquired data, andcan output data when needed and also provide control interface and control protocol sothat it can be controlled in real-time by other main devices. The whole system can bedivided into three parts: the interface module, the storage module, the high-speedbackplane.This paper generally focuses on the design and implementation of the interfacemodule of the system and the main work is as follows:(1) According to the system design requirements and technical details, a overallstructure of the whole system was put forward with the definition of the main interfacesand the basic function of the system. Give a detailed and strict demonstration on thedesign of all three modules.(2) Put forward the data path structure of the interface modules and give adescription of the design and implementation of each part in data path. Design the firstlevel cache of the data path and bring out a kind of data distribution mechanism. Highspeed serial communication between the interface module and storage module wasachieved.(3) Design a control scheme for the whole system. Analysis and comparison is madeamong different implementation plans of the physic interface. According to the plan, thecontrol interface and communication mechanism was put forward. Design the systemcommand set based on the general function of the system.At present, the basic function module of the system has been achieved and tested. Atthe end of this paper, some methods and suggestions to further improve the performanceof the system are put forward.
Keywords/Search Tags:Data acquisition, FPGA, Cache, Control mechanism, Transceiver
PDF Full Text Request
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