Research And Verification Of Verification Platform Based On PCI Express Interface

With the rapid development of the integrated circuit industry,the chip design scale has been greatly increased,and the development cycle has been continuously shortened.In order to ensure the reliability of the chip,higher requirements are required for chip verification.The traditional verification method has become a bottleneck for increasing the scale of chip design due to low efficiency and poor reliability.In order to solve this problem,the industry has proposed a verification methodology solution.After a period of improvement and development,the new generation of UVM(Universal Verification Methodology)has been widely recognized and promoted by the industry for its superior and highly efficient features.It can also ensure the reliability of verification quality to the greatest extent while shortening the verification cycle.To some extent represents the development direction of verification methodology.In addition,in order to further improve the portability,completeness,and verification efficiency of the verification platform,some design companines have put forward the concept of verification IP(Intellectual Property),providing a mature solution for a certain module and interface verification.As the third-generation bus protocol,the PCI Express(Peripheral Component Interconnect Express)bus protocol retains the advantages of the previous-generation PCI(Peripheral Component Interconnect)architecture and improves it.From the parallel architecture to the serial structure,and adopting the peer-to-peer interconnection method,the speed and performance have been greatly improved.The improvement of the interface and the increase of the application range of the interface make the verification requirements of the PCI Express interface more stringent.Therefore,it is necessary to build a verification platform that is more efficient and highly portable.This paper takes the PCI Express interface of the project as an entry point,conducts in-depth research around PCI Express bus technology and UVM verification methodology,and combines verification IP tools to develop a coverage-driven verification platform.From the verification environment analysis,the implementation of platform components and the VIP configuration,three aspects of the verification platform based on the transaction-level modeling method are discussed,and the decomposition method for the PCI Express interface function points is proposed.In addition,the automatic detection method of the verification results is studied and the effectiveness of the verification platform is evaluated.The results show that the verification platform can achieve the reusability of the incentive,the automation of the simulation operation and the reusability of the entire verification platform.This paper focuses on the detailed analysis of the PCI Express interface protocol,and discusses the logic level and the format of the data packet format of the PCI Express interface.Based on the characteristics of the layered design of the UVM methodology and the research on the verification IP,this paper proposes the verification strategy that meets the needs of the project,using the transaction-level modeling method based on the verification strategy to create the internal components of the platform,and complete the connection and debugging,eventually researched and designed a PCI Express verification platform that can achieve reusability and a high degree of automation.Compared with other traditional UVM environment platforms,this platform integrates verification IP components and can selectively configure environment components according to the actual needs of the project,further improving verification efficiency and increasing the reliability of verification results.In order to test the reliability of the verification platform studied in this paper,the function points of the PCI Express interface are extracted according to the design specification,effective incentives are programmed for simulation,and simulation waveforms are acquired through the monitor.Analysis of the simulation results shows that the verification results are consistent with the verification plan.The code coverage rate exceeds 90%,which reflects that the design code basically achieves maximum utilization and effectively reduces the time required for post-simulation,the functional coverage reaches 100%,which satisfies the comprehensive requirements of functional point inspection.The verification platform can effectively improve the efficiency of verification,reduce loopholes in the design process,and reduce the possibility of reflow.In addition,the verification platform has significant reference for the project team's future chip verification.