Design Of A Universal Verification Platform Compatible With Multimemory Host Controller

Universal Verification Methodology has now been widely used in the verification process of digital chips in the industry.It is necessary to design a matching verification platform and perform the functional verification process completely and effectively on the chip of the host controller,since the verification process of the host controller chip that supports three kinds of memory devices is complex and full of challenges and the existing verification platform only adapts to the host controller that supports single memory device.In view of the above situation,the three memory device protocols involved are studied,the design details of the host controller deeply analyzed,the test points are extracted,and a verification platform based on the universal verification methodology is built in this thesis.The interface design of the verification intellectual property core in the verification platform that only supports a single memory host controller has been improved.And the key verification components are incrementally developed to meet the requirements of compatibility with the three protocols.In addition,to optimize the subsequent version iterations,the callback mechanism,factory mechanism,configuration mechanism,etc.of the UVM are used to design common interfaces for the verification components in the thesis,thereby the reusability of the verification platform is improved.A reference model for simulating the functions of a host controller based on the System Verilog language is built in the thesis,and a comprehensive verification of the coverage-driven host controller for a compatible multi-memory host controller has been conducted.The verification platform built in this article has been successfully reused in subsequent iterations,and the reused code amount reached nearly 85%.In addition,after many iterative tests,the code coverage rate in the verification results of this thesis is higher than 98%,and the functional coverage rate reaches 100%,which all meet the design requirements and provide quality assurance for the success of the subsequent chip taping out.