Verification Of Bidirectional PCI Express Bridge Circuits

With the development of data communication in the chip,the first two generations of IO bus PCI and PCI-X have become increasingly unable to meet the communication speed requirements.The PCI Express bus is a third-generation high-speed serial IO bus released by the PCI-SIG.Unlike the parallel structure of the previous two generations of IO buses,the PCI Express bus has undergone a fundamental adjustment in its structure—using serial point-to-point dual-channel transmission.The PCI Express bus achieves higher frequencies,greater bandwidth,fewer pins,and smaller routing area than the shared bus bandwidth of the parallel bus architecture.When IO interconnects transition from PCI and PCI-X buses to PCI Express,bridge chips play an important role in bus interconnects: support for PCI and PCI-X buses in PCI Express-based systems.This thesis is written by me during my internship in a company,relying on the actual engineering project of the enterprise.The main work is to realize the verification of the bidirectional PCI Express bridge circuit.By carefully studying the chip structure function and the PCI Express,PCI,PCI-X bus protocol,the verification testbench is built.The functional simulation of the chip was carried out,and the design for test of the chip was verified by using the ATPG tool.This thesis first introduces the development of PCI Express bus,and analyzes the technical improvements made by PCI Express bus compared with PCI and PCI-X buses: using highspeed serial bus and point-to-point structure transmission,and expounding bridging key features of the three bus protocols supported by the chip.After analyzing the functional structure of the chip,in order to verify the correctness of the chip function and the inserted testability design,Synopsys' PCI Express VIP and Xilinx PCI-X IP were used to build a verification testbench,which greatly improved the verification's accuracy and efficiency.At the same time,it focuses on the Cfg read and write,Mem read and write and IO read and write functions of the bridge chip.The verification plan is prepared,and the corresponding testcases are written.The data transmission of the chip is simulated under different read and write modes.The typical modes and scenarios are selected,the waveforms are analyzed and the verification coverage is collected.In the verification of design for testability,the circuit must first be re-synthesized,generate new circuit netlist and scan chain constraints,and then use Synopsys' ATPG Tetra Max tool to automatically generate test vectors,testbench and test coverage.The scan chain are simulated by the generated testbench and test vectors and compare the output with the expected output of the tool to verify the correctness of the scan chain insertion.The final verification results show that the function of the chip and the design of the scan chain have met the target requirements.