Research On The Reusability Of Verification Platform

With the rapidly development of fabrication technology in integrated circuit, system-on-a-chip has become reality. But system-on-a-chip also brings us some challenges; one of the challenges is how to verify a system-on-a-chip. Verification has become the bottleneck in the integrated circuit and consumes about 70 percent in the whole chip design, what's more, with the standardization of the intellectual property, this trend is up, and so something must be done to alleviate the trend. In the design of system-on-a-chip, the number of the intellectual property reuse-based has become more and more. How to verify the intellectual property and the whole system-on-a-chip rapidly is becoming focus in the system-on-a-chip verification.This dissertation studies the reuse methodology in the verification, analyzes the intellectual property standalone verification platform, discusses the design methods of bus function model and bus monitor in the reusable function verification platform, investigate the difference in the reusability of the implementation mode of task-based and state machine-based bus function model and present the reusability design rules in the bus monitor. In the end discusses the design methodology of system-on-a-chip integration verification platform and analyzes some aspects, such as data organization, verification tools, system security and management, in detail.